Tubii_Tk2/Parts/parts/ttl/f74/entity/verilog.v
2015-02-27 19:09:38 -05:00

18 lines
229 B
Verilog

// generated by newgenasym Wed Jul 16 14:58:22 2014
module f74 (cl, cp, d, pr, q, \q* );
input cl;
input cp;
input d;
input pr;
output q;
output \q* ;
initial
begin
end
endmodule