15 lines
357 B
VHDL
15 lines
357 B
VHDL
-- generated by newgenasym Wed Jul 16 14:58:22 2014
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity f74 is
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port (
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CL: IN STD_LOGIC;
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CP: IN STD_LOGIC;
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D: IN STD_LOGIC;
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PR: IN STD_LOGIC;
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Q: OUT STD_LOGIC;
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\q*\: OUT STD_LOGIC);
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end f74;
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