15 lines
209 B
Verilog
15 lines
209 B
Verilog
// generated by newgenasym Wed Aug 20 16:01:43 2014
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module hct04 (a, \y* );
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parameter size = 1;
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input [size-1:0] a;
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output [size-1:0] \y* ;
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initial
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begin
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end
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endmodule
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