24 lines
252 B
Verilog
24 lines
252 B
Verilog
// Generated by Part Developer
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// Modified to support swift models
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`timescale 1ns/100ps
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module hct04 (\y* ,a);
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parameter size = 1;
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output [size-1:0] \y* ;
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input [size-1:0] a;
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SIG74hct04P inst1 [size-1:0]
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(
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a,
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\y*
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);
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endmodule
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