16 lines
201 B
Verilog
16 lines
201 B
Verilog
// generated by newgenasym Fri Aug 22 18:48:32 2014
|
|
|
|
|
|
module hct273 (clk, \clr* , d, q);
|
|
input clk;
|
|
input \clr* ;
|
|
input d;
|
|
output q;
|
|
|
|
|
|
initial
|
|
begin
|
|
end
|
|
|
|
endmodule
|