Tubii_Tk2/Parts/parts/ttl/hct273/entity/vhdl.vhd
2015-02-27 19:09:38 -05:00

13 lines
295 B
VHDL

-- generated by newgenasym Fri Aug 22 18:48:32 2014
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity hct273 is
port (
CLK: IN STD_LOGIC;
\clr*\: IN STD_LOGIC;
D: IN STD_LOGIC;
Q: OUT STD_LOGIC);
end hct273;