13 lines
295 B
VHDL
13 lines
295 B
VHDL
-- generated by newgenasym Fri Aug 22 18:48:32 2014
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity hct273 is
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port (
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CLK: IN STD_LOGIC;
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\clr*\: IN STD_LOGIC;
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D: IN STD_LOGIC;
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Q: OUT STD_LOGIC);
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end hct273;
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