Tubii_Tk2/worklib/baseline_buffer/sch_1/page1.csv
2015-06-04 15:18:08 -04:00

8.8 KiB

1FILE_TYPE = CONNECTIVITY;
2{Allegro Design Entry HDL 16.6-p007 (v16-6-112F) 10/10/2012}
3;
4B<0>
5A<0>
6;
7B<0>
8A<0>
9;
10A<0>
11B<0>
12;
13A<0>
14B<0>
15;
16A<0>
17B<0>
18;
19A<0>
20B<0>
21;
22A<0>
23B<0>
24;
25A<0>
26B<0>
27;
28A<0>
29B<0>
30;
31A<0>
32B<0>
33;
34A<0>
35B<0>
36;
37A<0>
38B<0>
39;
4014
4113
4212
4311
4410
459
468
477
486
495
504
513
522
531
54;
5514
5613
5712
5811
5910
609
618
627
636
645
654
663
672
681
69;
70+IN_A
71V-
72V+
73OUT_B
74+IN_C
75-IN_B
76-IN_A
77+IN_B
78OUT_C
79OUT_D
80OUT_A
81-IN_D
82+IN_D
83-IN_C
84;
85+IN_A
86V-
87V+
88OUT_B
89+IN_C
90-IN_B
91-IN_A
92+IN_B
93OUT_C
94OUT_D
95OUT_A
96-IN_D
97+IN_D
98-IN_C
99;
100+IN_A
101-IN_B
102-IN_A
103+IN_B
104V-
105V+
106OUT_B
107OUT_A
108;
109B<0>
110A<0>
111;
112B<0>
113A<0>
114;
115B<0>
116A<0>
117;
118B<0>
119A<0>
120END.