Tubii_Tk2/worklib/caen_coms/sch_1/page1.csv
2015-05-18 16:11:03 -04:00

4.2 KiB

1FILE_TYPE = CONNECTIVITY;
2{Allegro Design Entry HDL 16.6-p007 (v16-6-112F) 10/10/2012}
3;
4DATA_RDY
5LE
6CLK
7DATA
8PULSE_IN_ANAL<0..11>
9SCOPE_OUT_ANAL<0..7>
10CAEN_OUT_ANAL<0..7>
11;
12A
13;
14A
15;
16A
17;
18A
19;
20A
21;
22A
23;
24A
25;
26A
27;
28A
29;
30A
31;
32GT_TTL_OUT
33SYNC_P
34SYNC_N \B
35SYNC24_P
36SYNC24_N \B
37GT_P
38GT_N \B
39SYNC_LVDS_N \B
40SYNC_LVDS_P
41SYNC24_LVDS_N \B
42SYNC24_LVDS_P
43GT_NIM
44GT_TTL
45GT2_P
46GT2_N \B
47SYNC_TTL
48SYNC24_TTL
49;
50A
51;
52A
53;
54A
55;
56A
57;
58A
59;
60A
61;
62A
63;
64A
65;
66A
67;
68A
69;
70A
71;
72A
73;
74A
75;
76A
77END.