25 lines
484 B
Verilog
25 lines
484 B
Verilog
// generated by newgenasym Fri May 15 14:41:54 2015
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module clocks (bckp_used, clk100_n, clk100_p, clk100_ttl, clk_sel, data,
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data_rdy, le, reset, sr_clk, tub_clk_in_n, tub_clk_in_p);
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output bckp_used;
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output clk100_n;
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output clk100_p;
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output clk100_ttl;
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input clk_sel;
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input data;
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input data_rdy;
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input le;
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input reset;
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input sr_clk;
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input tub_clk_in_n;
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input tub_clk_in_p;
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initial
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begin
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end
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endmodule
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