21 lines
574 B
VHDL
21 lines
574 B
VHDL
-- generated by newgenasym Fri May 15 14:41:54 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity clocks is
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port (
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BCKP_USED: OUT STD_LOGIC;
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CLK100_N: OUT STD_LOGIC;
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CLK100_P: OUT STD_LOGIC;
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CLK100_TTL: OUT STD_LOGIC;
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CLK_SEL: IN STD_LOGIC;
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DATA: IN STD_LOGIC;
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DATA_RDY: IN STD_LOGIC;
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LE: IN STD_LOGIC;
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RESET: IN STD_LOGIC;
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SR_CLK: IN STD_LOGIC;
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TUB_CLK_IN_N: IN STD_LOGIC;
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TUB_CLK_IN_P: IN STD_LOGIC);
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end clocks;
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