Tubii_Tk2/worklib/clocks/sch_1/page1.csv

1	FILE_TYPE = CONNECTIVITY;
2	{Allegro Design Entry HDL 16.6-p007 (v16-6-112F) 10/10/2012}
3	;
4	TUB_CLK_IN_P
5	TUB_CLK_IN_N \B
6	CLK_SEL
7	RESET
8	DEFAULT_CLK
9	BCKP_CLK
10	RESET_ECL_P
11	;
12	B<0>
13	A<0>
14	;
15	B<0>
16	A<0>
17	;
18	B<0>
19	A<0>
20	;
21	B<0>
22	A<0>
23	;
24	;
25	A
26	;
27	B<0>
28	A<0>
29	;
30	A
31	;
32	A
33	;
34	A
35	;
36	BCKP_CLK3_N \B
37	BCKP_CLK3_P
38	BCKP_CLK2_N \B
39	BCKP_CLK2_P
40	DEFAULT_CLK2_N \B
41	DEFAULT_CLK2_P
42	CHANGE_CLK_N \B
43	BCKP_CLK
44	DEFAULT_CLK
45	CLK_RESET_TTL
46	CLK_RESET_ECL
47	DATA_RDY
48	MAX_COUNT<0..7>
49	CHANGE_CLK_P
50	;
51	A
52	;
53	A
54	;
55	A
56	;
57	A
58	;
59	A1
60	A2
61	B1
62	B2
63	;
64	GND
65	VCC
66	Y4
67	Y3
68	Y2
69	Y1
70	B4
71	B3
72	B2
73	B1
74	A4
75	A3
76	A2
77	A1
78	;
79	A<0>
80	B<0>
81	;
82	A
83	;
84	DSA
85	DSB
86	Q0
87	Q1
88	Q2
89	Q3
90	Q4
91	Q5
92	Q6
93	Q7
94	CP
95	GND
96	VCC
97	MR* \B
98	;
99	B<0>
100	A<0>
101	;
102	BCKP_USED
103	CLK100_TTL
104	CLK100_N \B
105	CLK100_P
106	BCKP_CLK3_N \B
107	BCKP_CLK3_P
108	BCKP_CLK2_N \B
109	BCKP_CLK2_P
110	DEFAULT_CLK2_N \B
111	DEFAULT_CLK2_P
112	CHANGE_CLK_N \B
113	CHANGE_CLK_P
114	;
115	A
116	;
117	A
118	;
119	A
120	;
121	COMMON
122	GND
123	VCC
124	VEE
125	D_OUT* \B
126	C_OUT* \B
127	B_OUT* \B
128	A_OUT* \B
129	D_OUT
130	C_OUT
131	B_OUT
132	A_OUT
133	D_IN
134	C_IN
135	B_IN
136	A_IN
137	;
138	COMMON
139	GND
140	VCC
141	VEE
142	D_OUT* \B
143	C_OUT* \B
144	B_OUT* \B
145	A_OUT* \B
146	D_OUT
147	C_OUT
148	B_OUT
149	A_OUT
150	D_IN
151	C_IN
152	B_IN
153	A_IN
154	END.