20 lines
372 B
Verilog
20 lines
372 B
Verilog
// generated by newgenasym Fri May 15 14:42:14 2015
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module default_clk_sel (bckp_clk, clk_sel, default_clk, reset, reset_ecl_p,
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tub_clk_in_n, tub_clk_in_p);
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output bckp_clk;
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input clk_sel;
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output default_clk;
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input reset;
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output reset_ecl_p;
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input tub_clk_in_n;
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input tub_clk_in_p;
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initial
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begin
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end
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endmodule
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