Eric Marzec de6bf2b612 Changed planes for POWER and added LVDS terminating res		2015-05-15 14:44:54 -04:00
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master.tag	Created CLK Picking schem	2015-03-01 15:28:37 -05:00
verilog.v	Changed planes for POWER and added LVDS terminating res	2015-05-15 14:44:54 -04:00
vhdl.vhd	Changed planes for POWER and added LVDS terminating res	2015-05-15 14:44:54 -04:00