16 lines
425 B
VHDL
16 lines
425 B
VHDL
-- generated by newgenasym Fri May 15 14:42:14 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity default_clk_sel is
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port (
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BCKP_CLK: OUT STD_LOGIC;
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CLK_SEL: IN STD_LOGIC;
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DEFAULT_CLK: OUT STD_LOGIC;
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RESET: IN STD_LOGIC;
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RESET_ECL_P: OUT STD_LOGIC;
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TUB_CLK_IN_N: IN STD_LOGIC;
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TUB_CLK_IN_P: IN STD_LOGIC);
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end default_clk_sel;
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