Tubii_Tk2/worklib/ecal_control/sch_1/page1.csv

1	FILE_TYPE = CONNECTIVITY;
2	{Allegro Design Entry HDL 16.6-p007 (v16-6-112F) 10/10/2012}
3	;
4	COMMON
5	GND
6	VCC
7	VEE
8	D_OUT* \B
9	C_OUT* \B
10	B_OUT* \B
11	A_OUT* \B
12	D_OUT
13	C_OUT
14	B_OUT
15	A_OUT
16	D_IN
17	C_IN
18	B_IN
19	A_IN
20	;
21	A
22	;
23	A
24	;
25	A
26	;
27	A
28	;
29	B<0>
30	A<0>
31	;
32	B<0>
33	A<0>
34	;
35	B<0>
36	A<0>
37	;
38	A<0>
39	B<0>
40	;
41	VEE
42	GND2
43	GND1
44	Q4* \B
45	Q4
46	Q3
47	Q2
48	Q1
49	B4
50	B3
51	B2
52	B1
53	A4
54	A3
55	A2
56	A1
57	;
58	A\NAC
59	B\NAC
60	;
61	A<0>
62	B<0>
63	;
64	A<0>
65	B<0>
66	;
67	A<0>
68	B<0>
69	END.