Tubii_Tk2/worklib/general_utilities/sch_1/page1.csv

5.0 KiB

1FILE_TYPE = CONNECTIVITY;
2{Allegro Design Entry HDL 16.6-p007 (v16-6-112F) 10/10/2012}
3;
4PULSE_INV_OUT
5PULSE_INV_IN
6;
7A
8;
9A
10;
11A
12;
13A
14;
15A
16;
17A
18;
19A
20;
21A
22;
23A
24;
25PULSE_OUT_N \B
26PULSE_OUT_P
27PULSE_IN_N \B
28PULSE_IN_P
29;
30LVDS_TO_ECL_OUT
31TTL_TO_ECL_OUT
32NIM_TO_ECL_IN
33LVDS_TO_ECL_IN_N \B
34LVDS_TO_ECL_IN_P
35TTL_TO_ECL_IN
36ECL_TO_NIM_IN
37ECL_TO_LVDS_IN
38ECL_TO_TTL_IN
39NIM_TO_ECL_OUT
40ECL_TO_TTL_OUT
41ECL_TO_LVDS_OUT_P
42ECL_TO_LVDS_OUT_N \B
43ECL_TO_NIM_OUT
44;
45A
46;
47A
48;
49A
50;
51A
52;
53A
54;
55A
56;
57A
58;
59A
60;
61A
62;
63A
64;
65A
66;
67A
68;
69A
70;
71A
72;
73DELAY_OUT
74PULSE_OUT
75DELAY_IN
76PULSE_IN
77LE
78CLK
79DATA
80;
81A
82;
83A
84;
85A
86;
87A
88END.