Tubii_Tk2/worklib/generic_delays/sch_1/page1.csv
2015-06-04 15:18:08 -04:00

6.9 KiB

1FILE_TYPE = CONNECTIVITY;
2{Allegro Design Entry HDL 16.6-p007 (v16-6-112F) 10/10/2012}
3;
4VCC
5GND
6D/P2
7CLK/P1
8Q/P0
9P7
10P6
11P5
12P4
13P3
14IN
15PS
16MS
17OUT
18PWM
19LE* \B
20;
21A
22;
23A
24;
25A
26;
27B<0>
28A<0>
29;
30B<0>
31A<0>
32;
33A<0>
34B<0>
35;
36A<0>
37B<0>
38;
39A\NAC
40B\NAC
41;
42A\NAC
43B\NAC
44;
45A<0>
46B<0>
47;
48B<0>
49A<0>
50;
51A<0>
52B<0>
53;
54B<0>
55A<0>
56;
57GND
58VCC
59IN_B2
60IN_B1
61IN_A2* \B
62IN_A1* \B
63REXT/CEXT2
64REXT/CEXT1
65CEXT2
66CEXT1
67Q2* \B
68Q1* \B
69Q2
70Q1
71RD2* \B
72RD1* \B
73;
74VCC
75GND
76D/P2
77CLK/P1
78Q/P0
79P7
80P6
81P5
82P4
83P3
84IN
85PS
86MS
87OUT
88PWM
89LE* \B
90;
91B<0>
92A<0>
93;
94A
95;
96A
97;
98A
99;
100A
101END.