6.9 KiB
6.9 KiB
1 | FILE_TYPE = CONNECTIVITY; |
---|---|
2 | {Allegro Design Entry HDL 16.6-p007 (v16-6-112F) 10/10/2012} |
3 | ; |
4 | VCC |
5 | GND |
6 | D/P2 |
7 | CLK/P1 |
8 | Q/P0 |
9 | P7 |
10 | P6 |
11 | P5 |
12 | P4 |
13 | P3 |
14 | IN |
15 | PS |
16 | MS |
17 | OUT |
18 | PWM |
19 | LE* \B |
20 | ; |
21 | A |
22 | ; |
23 | A |
24 | ; |
25 | A |
26 | ; |
27 | B<0> |
28 | A<0> |
29 | ; |
30 | B<0> |
31 | A<0> |
32 | ; |
33 | A<0> |
34 | B<0> |
35 | ; |
36 | A<0> |
37 | B<0> |
38 | ; |
39 | A\NAC |
40 | B\NAC |
41 | ; |
42 | A\NAC |
43 | B\NAC |
44 | ; |
45 | A<0> |
46 | B<0> |
47 | ; |
48 | B<0> |
49 | A<0> |
50 | ; |
51 | A<0> |
52 | B<0> |
53 | ; |
54 | B<0> |
55 | A<0> |
56 | ; |
57 | GND |
58 | VCC |
59 | IN_B2 |
60 | IN_B1 |
61 | IN_A2* \B |
62 | IN_A1* \B |
63 | REXT/CEXT2 |
64 | REXT/CEXT1 |
65 | CEXT2 |
66 | CEXT1 |
67 | Q2* \B |
68 | Q1* \B |
69 | Q2 |
70 | Q1 |
71 | RD2* \B |
72 | RD1* \B |
73 | ; |
74 | VCC |
75 | GND |
76 | D/P2 |
77 | CLK/P1 |
78 | Q/P0 |
79 | P7 |
80 | P6 |
81 | P5 |
82 | P4 |
83 | P3 |
84 | IN |
85 | PS |
86 | MS |
87 | OUT |
88 | PWM |
89 | LE* \B |
90 | ; |
91 | B<0> |
92 | A<0> |
93 | ; |
94 | A |
95 | ; |
96 | A |
97 | ; |
98 | A |
99 | ; |
100 | A |
101 | END. |