Tubii_Tk2/worklib/gt_delays/sch_1/page1.csv
2015-06-04 15:18:08 -04:00

8.4 KiB

1FILE_TYPE = CONNECTIVITY;
2{Allegro Design Entry HDL 16.6-p007 (v16-6-112F) 10/10/2012}
3;
4VCC
5GND
6IN
7PWM
8OUT
9P3
10P4
11D/P2
12PS
13CLK/P1
14LE* \B
15Q/P0
16MS
17P5
18P6
19P7
20;
21COMMON
22GND
23VCC
24VEE
25D_OUT* \B
26C_OUT* \B
27B_OUT* \B
28A_OUT* \B
29D_OUT
30C_OUT
31B_OUT
32A_OUT
33D_IN
34C_IN
35B_IN
36A_IN
37;
38B<0>
39A<0>
40;
41B<0>
42A<0>
43;
44B<0>
45A<0>
46;
47B<0>
48A<0>
49;
50B<0>
51A<0>
52;
53A<0>
54B<0>
55;
56A<0>
57B<0>
58;
59A\NAC
60B\NAC
61;
62A\NAC
63B\NAC
64;
65A<0>
66B<0>
67;
68A<0>
69B<0>
70;
71A
72;
73A
74;
75A
76;
77A
78;
79GND
80VCC
81IN
82Q/P0
83P4
84P3
85CLK/P1
86D/P2
87P7
88P6
89P5
90MS
91PS
92PWM
93OUT
94LE* \B
95;
96A
97;
98A
99;
100B<0>
101A<0>
102;
103B<0>
104A<0>
105;
106A
107;
108A
109;
110A
111;
112GND
113VCC
114IN_B2
115IN_B1
116IN_A2* \B
117IN_A1* \B
118REXT/CEXT2
119REXT/CEXT1
120CEXT2
121CEXT1
122Q2* \B
123Q1* \B
124Q2
125Q1
126RD2* \B
127RD1* \B
128END.