Tubii_Tk2/worklib/pulse_inverter/sch_1/page1.csv

1	FILE_TYPE = CONNECTIVITY;
2	{Allegro Design Entry HDL 16.6-p007 (v16-6-112F) 10/10/2012}
3	;
4	V+
5	V-
6	OUTPUT
7	IN+
8	IN-
9	;
10	A<0>
11	B<0>
12	;
13	B<0>
14	A<0>
15	;
16	B<0>
17	A<0>
18	;
19	B<0>
20	A<0>
21	;
22	A<0>
23	B<0>
24	;
25	A<0>
26	B<0>
27	;
28	A
29	;
30	A
31	;
32	B<0>
33	A<0>
34	;
35	A<0>
36	B<0>
37	END.