Tubii_Tk2/worklib/translation/sch_1/translation.xcon,1
Eric Marzec ac5895baa3 Worked on translation schems and...
Something is wrong with the translation block symbol. I'm
gonna try and fix it without deleting everything but this commit
is just in case i fuck that up
2015-03-04 18:45:16 -05:00

2298 lines
62 KiB
Plaintext

<schema xmlns="http://www.cadence.com/spb/csschema"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.cadence.com/spb/csschema CSSchema002.xsd">
<header>
<schemaVersion>16.6</schemaVersion>
<creatorTool>conceptHDL</creatorTool>
<modifierTool>conceptHDL</modifierTool>
<modificationTime>2015-03-04T18:12:46</modificationTime>
<savedLibrary>tubii_tk2_lib</savedLibrary>
</header>
<designs>
<design schemaType="nameBased" name="translation" view="sch_1">
<external_errors>true</external_errors>
<lastids>
<instanceid>27</instanceid>
<netid>40</netid>
<insttermid>148</insttermid>
</lastids>
<cells>
<cell>
<id>S2</id>
<library>tubii_tk2_lib</library>
<name>ttl_ecl</name>
<view>sym_1</view>
<parameters>
</parameters>
<terms>
<term>
<id>T1</id>
<name>ecl_in_n</name>
<direction>input</direction>
</term>
<term>
<id>T2</id>
<name>ecl_in_p</name>
<direction>input</direction>
</term>
<term>
<id>T3</id>
<name>ecl_out_n</name>
<direction>output</direction>
</term>
<term>
<id>T4</id>
<name>ecl_out_p</name>
<direction>output</direction>
</term>
<term>
<id>T5</id>
<name>ttl_in</name>
<direction>input</direction>
</term>
<term>
<id>T6</id>
<name>ttl_out</name>
<direction>output</direction>
</term>
</terms>
</cell>
<cell>
<id>S3</id>
<library>tubii_tk2_lib</library>
<name>lvds_ecl</name>
<view>sym_1</view>
<parameters>
</parameters>
<terms>
</terms>
</cell>
<cell>
<id>S4</id>
<library>tubii_tk2_lib</library>
<name>nim_ecl</name>
<view>sym_1</view>
<parameters>
</parameters>
<terms>
</terms>
</cell>
<cell>
<id>S6</id>
<library>capacitors</library>
<name>csmd0805</name>
<view>sym_1</view>
<parameters>
</parameters>
<terms>
<term>
<id>T25</id>
<name>a</name>
<direction>input</direction>
<msb>0</msb>
<lsb>0</lsb>
</term>
<term>
<id>T26</id>
<name>b</name>
<direction>output</direction>
<msb>0</msb>
<lsb>0</lsb>
</term>
</terms>
</cell>
<cell>
<id>S7</id>
<library>ecl</library>
<name>mc10h125</name>
<view>sym_1</view>
<parameters>
</parameters>
<terms>
<term>
<id>T27</id>
<name>d1</name>
<direction>input</direction>
</term>
<term>
<id>T28</id>
<name>d1*</name>
<direction>input</direction>
</term>
<term>
<id>T29</id>
<name>d2</name>
<direction>input</direction>
</term>
<term>
<id>T30</id>
<name>d2*</name>
<direction>input</direction>
</term>
<term>
<id>T31</id>
<name>d3</name>
<direction>input</direction>
</term>
<term>
<id>T32</id>
<name>d3*</name>
<direction>input</direction>
</term>
<term>
<id>T33</id>
<name>d4</name>
<direction>input</direction>
</term>
<term>
<id>T34</id>
<name>d4*</name>
<direction>input</direction>
</term>
<term>
<id>T35</id>
<name>gnd</name>
<direction>input</direction>
</term>
<term>
<id>T36</id>
<name>q1</name>
<direction>output</direction>
</term>
<term>
<id>T37</id>
<name>q2</name>
<direction>output</direction>
</term>
<term>
<id>T38</id>
<name>q3</name>
<direction>output</direction>
</term>
<term>
<id>T39</id>
<name>q4</name>
<direction>output</direction>
</term>
<term>
<id>T40</id>
<name>vbb</name>
<direction>output</direction>
</term>
<term>
<id>T41</id>
<name>vcc</name>
<direction>input</direction>
</term>
<term>
<id>T42</id>
<name>vee</name>
<direction>input</direction>
</term>
</terms>
</cell>
<cell>
<id>S8</id>
<library>ecl</library>
<name>mc10h124</name>
<view>sym_1</view>
<parameters>
</parameters>
<terms>
<term>
<id>T43</id>
<name>a_in</name>
<direction>input</direction>
</term>
<term>
<id>T44</id>
<name>a_out</name>
<direction>output</direction>
</term>
<term>
<id>T45</id>
<name>a_out*</name>
<direction>output</direction>
</term>
<term>
<id>T46</id>
<name>b_in</name>
<direction>input</direction>
</term>
<term>
<id>T47</id>
<name>b_out</name>
<direction>output</direction>
</term>
<term>
<id>T48</id>
<name>b_out*</name>
<direction>output</direction>
</term>
<term>
<id>T49</id>
<name>c_in</name>
<direction>input</direction>
</term>
<term>
<id>T50</id>
<name>c_out</name>
<direction>output</direction>
</term>
<term>
<id>T51</id>
<name>c_out*</name>
<direction>output</direction>
</term>
<term>
<id>T52</id>
<name>common</name>
<direction>input</direction>
</term>
<term>
<id>T53</id>
<name>d_in</name>
<direction>input</direction>
</term>
<term>
<id>T54</id>
<name>d_out</name>
<direction>output</direction>
</term>
<term>
<id>T55</id>
<name>d_out*</name>
<direction>output</direction>
</term>
<term>
<id>T56</id>
<name>gnd</name>
<direction>input</direction>
</term>
<term>
<id>T57</id>
<name>vcc</name>
<direction>input</direction>
</term>
<term>
<id>T58</id>
<name>vee</name>
<direction>input</direction>
</term>
</terms>
</cell>
<cell>
<id>S9</id>
<library>misc</library>
<name>ds90lv019</name>
<view>sym_1</view>
<parameters>
</parameters>
<terms>
<term>
<id>T59</id>
<name>de</name>
<direction>input</direction>
</term>
<term>
<id>T60</id>
<name>din</name>
<direction>input</direction>
</term>
<term>
<id>T61</id>
<name>dout</name>
<direction>output</direction>
</term>
<term>
<id>T62</id>
<name>dout*</name>
<direction>output</direction>
</term>
<term>
<id>T63</id>
<name>gnd</name>
<direction>input</direction>
</term>
<term>
<id>T64</id>
<name>re</name>
<direction>input</direction>
</term>
<term>
<id>T65</id>
<name>ri</name>
<direction>input</direction>
</term>
<term>
<id>T66</id>
<name>ri*</name>
<direction>input</direction>
</term>
<term>
<id>T67</id>
<name>rout</name>
<direction>output</direction>
</term>
<term>
<id>T68</id>
<name>vcc</name>
<direction>input</direction>
</term>
</terms>
</cell>
<cell>
<id>S10</id>
<library>transistors</library>
<name>mpsh81</name>
<view>sym_1</view>
<parameters>
</parameters>
<terms>
<term>
<id>T72</id>
<name>b</name>
<direction>inout</direction>
</term>
<term>
<id>T73</id>
<name>c</name>
<direction>inout</direction>
</term>
<term>
<id>T74</id>
<name>e</name>
<direction>inout</direction>
</term>
</terms>
</cell>
<cell>
<id>S11</id>
<library>resistors</library>
<name>rsmd0805</name>
<view>sym_1</view>
<parameters>
</parameters>
<terms>
<term>
<id>T75</id>
<name>a</name>
<direction>input</direction>
<msb>0</msb>
<lsb>0</lsb>
</term>
<term>
<id>T76</id>
<name>b</name>
<direction>output</direction>
<msb>0</msb>
<lsb>0</lsb>
</term>
</terms>
</cell>
<cell>
<id>S12</id>
<library>transistors</library>
<name>mmbth10</name>
<view>sym_1</view>
<parameters>
</parameters>
<terms>
<term>
<id>T77</id>
<name>b</name>
<direction>inout</direction>
</term>
<term>
<id>T78</id>
<name>c</name>
<direction>inout</direction>
</term>
<term>
<id>T79</id>
<name>e</name>
<direction>inout</direction>
</term>
</terms>
</cell>
<cell>
<id>S13</id>
<library>ecl</library>
<name>mc10e116</name>
<view>sym_1</view>
<parameters>
</parameters>
<terms>
<term>
<id>T80</id>
<name>d0</name>
<direction>input</direction>
</term>
<term>
<id>T81</id>
<name>d0*</name>
<direction>input</direction>
</term>
<term>
<id>T82</id>
<name>d1</name>
<direction>input</direction>
</term>
<term>
<id>T83</id>
<name>d1*</name>
<direction>input</direction>
</term>
<term>
<id>T84</id>
<name>d2</name>
<direction>input</direction>
</term>
<term>
<id>T85</id>
<name>d2*</name>
<direction>input</direction>
</term>
<term>
<id>T86</id>
<name>d3</name>
<direction>input</direction>
</term>
<term>
<id>T87</id>
<name>d3*</name>
<direction>input</direction>
</term>
<term>
<id>T88</id>
<name>d4</name>
<direction>input</direction>
</term>
<term>
<id>T89</id>
<name>d4*</name>
<direction>input</direction>
</term>
<term>
<id>T90</id>
<name>gnd0</name>
<direction>input</direction>
</term>
<term>
<id>T91</id>
<name>gnd1</name>
<direction>input</direction>
</term>
<term>
<id>T92</id>
<name>gnd2</name>
<direction>input</direction>
</term>
<term>
<id>T93</id>
<name>gnd3</name>
<direction>input</direction>
</term>
<term>
<id>T94</id>
<name>gnd4</name>
<direction>input</direction>
</term>
<term>
<id>T95</id>
<name>gnd5</name>
<direction>input</direction>
</term>
<term>
<id>T96</id>
<name>q0</name>
<direction>output</direction>
</term>
<term>
<id>T97</id>
<name>q0*</name>
<direction>output</direction>
</term>
<term>
<id>T98</id>
<name>q1</name>
<direction>output</direction>
</term>
<term>
<id>T99</id>
<name>q1*</name>
<direction>output</direction>
</term>
<term>
<id>T100</id>
<name>q2</name>
<direction>output</direction>
</term>
<term>
<id>T101</id>
<name>q2*</name>
<direction>output</direction>
</term>
<term>
<id>T102</id>
<name>q3</name>
<direction>output</direction>
</term>
<term>
<id>T103</id>
<name>q3*</name>
<direction>output</direction>
</term>
<term>
<id>T104</id>
<name>q4</name>
<direction>output</direction>
</term>
<term>
<id>T105</id>
<name>q4*</name>
<direction>output</direction>
</term>
<term>
<id>T106</id>
<name>vbb</name>
<direction>output</direction>
</term>
<term>
<id>T107</id>
<name>vee</name>
<direction>input</direction>
</term>
</terms>
</cell>
<cell>
<id>S14</id>
<library>capacitors</library>
<name>csmd0603</name>
<view>sym_1</view>
<parameters>
</parameters>
<terms>
<term>
<id>T108</id>
<name>a</name>
<direction>input</direction>
<msb>0</msb>
<lsb>0</lsb>
</term>
<term>
<id>T109</id>
<name>b</name>
<direction>output</direction>
<msb>0</msb>
<lsb>0</lsb>
</term>
</terms>
</cell>
</cells>
<nets>
<net>
<id>N5</id>
<name>lvds_to_ecl_out_n</name>
<scope>interface</scope>
<direction>output</direction>
</net>
<net>
<id>N6</id>
<name>lvds_to_ecl_out_p</name>
<scope>interface</scope>
<direction>output</direction>
</net>
<net>
<id>N7</id>
<name>unnamed_1_csmd0805_i10_a</name>
</net>
<net>
<id>N8</id>
<name>unnamed_1_csmd0805_i10_b</name>
</net>
<net>
<id>N9</id>
<name>unnamed_1_csmd0805_i13_a</name>
</net>
<net>
<id>N10</id>
<name>unnamed_1_csmd0805_i13_b</name>
</net>
<net>
<id>N11</id>
<name>unnamed_1_csmd0805_i14_b</name>
</net>
<net>
<id>N12</id>
<name>unnamed_1_csmd0805_i9_b</name>
</net>
<net>
<id>N13</id>
<name>unnamed_1_ds90lv019_i15_rout</name>
</net>
<net>
<id>N16</id>
<name>ecl_to_lvds_in</name>
<scope>interface</scope>
<direction>input</direction>
</net>
<net>
<id>N17</id>
<name>ecl_to_lvds_out_n</name>
</net>
<net>
<id>N18</id>
<name>ecl_to_lvds_out_p</name>
</net>
<net>
<id>N19</id>
<name>ecl_to_nim_in</name>
<scope>interface</scope>
<direction>input</direction>
</net>
<net>
<id>N20</id>
<name>ecl_to_ttl_in</name>
<scope>interface</scope>
<direction>input</direction>
</net>
<net>
<id>N21</id>
<name>ecl_to_ttl_out</name>
<scope>interface</scope>
<direction>output</direction>
</net>
<net>
<id>N22</id>
<name>lvds_to_ecl_in_n</name>
</net>
<net>
<id>N23</id>
<name>lvds_to_ecl_in_p</name>
</net>
<net>
<id>N24</id>
<name>ttl_to_ecl_in</name>
<scope>interface</scope>
<direction>input</direction>
</net>
<net>
<id>N25</id>
<name>ttl_to_ecl_out_n</name>
<scope>interface</scope>
<direction>output</direction>
</net>
<net>
<id>N26</id>
<name>ttl_to_ecl_out_p</name>
<scope>interface</scope>
<direction>output</direction>
</net>
<net>
<id>N27</id>
<name>unnamed_1_ds90lv019_i15_din</name>
</net>
<net>
<id>N28</id>
<name>ecl_to_nim_out</name>
<scope>interface</scope>
<direction>output</direction>
</net>
<net>
<id>N29</id>
<name>nim_to_ecl_in</name>
</net>
<net>
<id>N30</id>
<name>nim_to_ecl_out</name>
</net>
<net>
<id>N31</id>
<name>unnamed_1_mc10e116_i30_d0</name>
</net>
<net>
<id>N32</id>
<name>unnamed_1_mc10e116_i30_d3</name>
</net>
<net>
<id>N33</id>
<name>unnamed_1_mc10e116_i30_q0</name>
</net>
<net>
<id>N34</id>
<name>unnamed_1_mc10e116_i30_q0_1</name>
</net>
<net>
<id>N35</id>
<name>unnamed_1_mc10e116_i30_q1</name>
</net>
<net>
<id>N36</id>
<name>unnamed_1_mc10e116_i30_q1_1</name>
</net>
<net>
<id>N37</id>
<name>unnamed_1_mc10e116_i30_q2</name>
</net>
<net>
<id>N38</id>
<name>unnamed_1_mpsh81_i17_c</name>
</net>
<net>
<id>N39</id>
<name>unnamed_1_rsmd0805_i20_a</name>
</net>
<net>
<id>N4</id>
<name>gnd</name>
<scope>global</scope>
</net>
<net>
<id>N15</id>
<name>vcc</name>
<scope>global</scope>
</net>
<net>
<id>N40</id>
<name>vee</name>
<scope>global</scope>
</net>
</nets>
<aliases>
</aliases>
<differentialnets>
</differentialnets>
<differentialbusnets>
</differentialbusnets>
<netgroups>
</netgroups>
<netinterfaces>
</netinterfaces>
<instances>
<instance>
<id>I1</id>
<cellid>S2</cellid>
<name>page1_i1</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M1</id>
<termid>T1</termid>
<connections>
</connections>
</pin>
<pin>
<id>M2</id>
<termid>T2</termid>
<connections>
</connections>
</pin>
<pin>
<id>M3</id>
<termid>T3</termid>
<connections>
</connections>
</pin>
<pin>
<id>M4</id>
<termid>T4</termid>
<connections>
</connections>
</pin>
<pin>
<id>M5</id>
<termid>T5</termid>
<connections>
</connections>
</pin>
<pin>
<id>M6</id>
<termid>T6</termid>
<connections>
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I2</id>
<cellid>S3</cellid>
<name>page1_i2</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I3</id>
<cellid>S4</cellid>
<name>page1_i3</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I6</id>
<cellid>S6</cellid>
<name>page1_i9</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M39</id>
<termid>T25</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N8" />
</connections>
</pin>
<pin>
<id>M40</id>
<termid>T26</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N12" />
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I7</id>
<cellid>S6</cellid>
<name>page1_i10</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M41</id>
<termid>T25</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N7" />
</connections>
</pin>
<pin>
<id>M42</id>
<termid>T26</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N8" />
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I8</id>
<cellid>S7</cellid>
<name>page1_i11</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M43</id>
<termid>T27</termid>
<connections>
<connection net="N33" />
</connections>
</pin>
<pin>
<id>M44</id>
<termid>T28</termid>
<connections>
<connection net="N34" />
</connections>
</pin>
<pin>
<id>M45</id>
<termid>T29</termid>
<connections>
<connection net="N36" />
</connections>
</pin>
<pin>
<id>M46</id>
<termid>T30</termid>
<connections>
<connection net="N35" />
</connections>
</pin>
<pin>
<id>M47</id>
<termid>T31</termid>
<connections>
</connections>
</pin>
<pin>
<id>M48</id>
<termid>T32</termid>
<connections>
</connections>
</pin>
<pin>
<id>M49</id>
<termid>T33</termid>
<connections>
</connections>
</pin>
<pin>
<id>M50</id>
<termid>T34</termid>
<connections>
</connections>
</pin>
<pin>
<id>M51</id>
<termid>T35</termid>
<connections>
<connection net="N8" />
</connections>
</pin>
<pin>
<id>M52</id>
<termid>T36</termid>
<connections>
<connection net="N21" />
</connections>
</pin>
<pin>
<id>M53</id>
<termid>T37</termid>
<connections>
<connection net="N27" />
</connections>
</pin>
<pin>
<id>M54</id>
<termid>T38</termid>
<connections>
</connections>
</pin>
<pin>
<id>M55</id>
<termid>T39</termid>
<connections>
</connections>
</pin>
<pin>
<id>M56</id>
<termid>T40</termid>
<connections>
</connections>
</pin>
<pin>
<id>M57</id>
<termid>T41</termid>
<connections>
<connection net="N12" />
</connections>
</pin>
<pin>
<id>M58</id>
<termid>T42</termid>
<connections>
<connection net="N7" />
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I9</id>
<cellid>S8</cellid>
<name>page1_i12</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M59</id>
<termid>T43</termid>
<connections>
<connection net="N24" />
</connections>
</pin>
<pin>
<id>M60</id>
<termid>T44</termid>
<connections>
<connection net="N26" />
</connections>
</pin>
<pin>
<id>M61</id>
<termid>T45</termid>
<connections>
<connection net="N25" />
</connections>
</pin>
<pin>
<id>M62</id>
<termid>T46</termid>
<connections>
<connection net="N13" />
</connections>
</pin>
<pin>
<id>M63</id>
<termid>T47</termid>
<connections>
<connection net="N6" />
</connections>
</pin>
<pin>
<id>M64</id>
<termid>T48</termid>
<connections>
<connection net="N5" />
</connections>
</pin>
<pin>
<id>M65</id>
<termid>T49</termid>
<connections>
</connections>
</pin>
<pin>
<id>M66</id>
<termid>T50</termid>
<connections>
</connections>
</pin>
<pin>
<id>M67</id>
<termid>T51</termid>
<connections>
</connections>
</pin>
<pin>
<id>M68</id>
<termid>T52</termid>
<connections>
<connection net="N15" />
</connections>
</pin>
<pin>
<id>M69</id>
<termid>T53</termid>
<connections>
</connections>
</pin>
<pin>
<id>M70</id>
<termid>T54</termid>
<connections>
</connections>
</pin>
<pin>
<id>M71</id>
<termid>T55</termid>
<connections>
</connections>
</pin>
<pin>
<id>M72</id>
<termid>T56</termid>
<connections>
<connection net="N10" />
</connections>
</pin>
<pin>
<id>M73</id>
<termid>T57</termid>
<connections>
<connection net="N9" />
</connections>
</pin>
<pin>
<id>M74</id>
<termid>T58</termid>
<connections>
<connection net="N11" />
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I10</id>
<cellid>S6</cellid>
<name>page1_i13</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M75</id>
<termid>T25</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N9" />
</connections>
</pin>
<pin>
<id>M76</id>
<termid>T26</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N10" />
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I11</id>
<cellid>S6</cellid>
<name>page1_i14</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M77</id>
<termid>T25</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N10" />
</connections>
</pin>
<pin>
<id>M78</id>
<termid>T26</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N11" />
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I12</id>
<cellid>S9</cellid>
<name>page1_i15</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M79</id>
<termid>T59</termid>
<connections>
<connection net="N15" />
</connections>
</pin>
<pin>
<id>M80</id>
<termid>T60</termid>
<connections>
<connection net="N27" />
</connections>
</pin>
<pin>
<id>M81</id>
<termid>T61</termid>
<connections>
<connection net="N18" />
</connections>
</pin>
<pin>
<id>M82</id>
<termid>T62</termid>
<connections>
<connection net="N17" />
</connections>
</pin>
<pin>
<id>M83</id>
<termid>T63</termid>
<connections>
<connection net="N4" />
</connections>
</pin>
<pin>
<id>M84</id>
<termid>T64</termid>
<connections>
<connection net="N4" />
</connections>
</pin>
<pin>
<id>M85</id>
<termid>T65</termid>
<connections>
<connection net="N23" />
</connections>
</pin>
<pin>
<id>M86</id>
<termid>T66</termid>
<connections>
<connection net="N22" />
</connections>
</pin>
<pin>
<id>M87</id>
<termid>T67</termid>
<connections>
<connection net="N13" />
</connections>
</pin>
<pin>
<id>M88</id>
<termid>T68</termid>
<connections>
<connection net="N15" />
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I13</id>
<cellid>S6</cellid>
<name>page1_i16</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M89</id>
<termid>T25</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N4" />
</connections>
</pin>
<pin>
<id>M90</id>
<termid>T26</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N15" />
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I14</id>
<cellid>S10</cellid>
<name>page1_i17</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M93</id>
<termid>T72</termid>
<connections>
<connection net="N37" />
</connections>
</pin>
<pin>
<id>M94</id>
<termid>T73</termid>
<connections>
<connection net="N38" />
</connections>
</pin>
<pin>
<id>M95</id>
<termid>T74</termid>
<connections>
<connection net="N28" />
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I15</id>
<cellid>S11</cellid>
<name>page1_i18</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M96</id>
<termid>T75</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N40" />
</connections>
</pin>
<pin>
<id>M97</id>
<termid>T76</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N38" />
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I16</id>
<cellid>S11</cellid>
<name>page1_i20</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M98</id>
<termid>T75</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N39" />
</connections>
</pin>
<pin>
<id>M99</id>
<termid>T76</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N20" />
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I17</id>
<cellid>S11</cellid>
<name>page1_i21</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M100</id>
<termid>T75</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N39" />
</connections>
</pin>
<pin>
<id>M101</id>
<termid>T76</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N16" />
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I18</id>
<cellid>S11</cellid>
<name>page1_i22</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M102</id>
<termid>T75</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N39" />
</connections>
</pin>
<pin>
<id>M103</id>
<termid>T76</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N19" />
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I19</id>
<cellid>S11</cellid>
<name>page1_i23</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M104</id>
<termid>T75</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N39" />
</connections>
</pin>
<pin>
<id>M105</id>
<termid>T76</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N33" />
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I20</id>
<cellid>S11</cellid>
<name>page1_i24</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M106</id>
<termid>T75</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N39" />
</connections>
</pin>
<pin>
<id>M107</id>
<termid>T76</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N36" />
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I21</id>
<cellid>S11</cellid>
<name>page1_i25</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M108</id>
<termid>T75</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N39" />
</connections>
</pin>
<pin>
<id>M109</id>
<termid>T76</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N34" />
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I22</id>
<cellid>S11</cellid>
<name>page1_i26</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M110</id>
<termid>T75</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N39" />
</connections>
</pin>
<pin>
<id>M111</id>
<termid>T76</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N35" />
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I23</id>
<cellid>S11</cellid>
<name>page1_i27</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M112</id>
<termid>T75</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N39" />
</connections>
</pin>
<pin>
<id>M113</id>
<termid>T76</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N37" />
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I24</id>
<cellid>S12</cellid>
<name>page1_i28</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M114</id>
<termid>T77</termid>
<connections>
<connection net="N29" />
</connections>
</pin>
<pin>
<id>M115</id>
<termid>T78</termid>
<connections>
<connection net="N4" />
</connections>
</pin>
<pin>
<id>M116</id>
<termid>T79</termid>
<connections>
<connection net="N32" />
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I25</id>
<cellid>S11</cellid>
<name>page1_i29</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M117</id>
<termid>T75</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N40" />
</connections>
</pin>
<pin>
<id>M118</id>
<termid>T76</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N32" />
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I26</id>
<cellid>S13</cellid>
<name>page1_i30</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M119</id>
<termid>T80</termid>
<connections>
<connection net="N20" />
</connections>
</pin>
<pin>
<id>M120</id>
<termid>T81</termid>
<connections>
<connection net="N31" />
</connections>
</pin>
<pin>
<id>M121</id>
<termid>T82</termid>
<connections>
<connection net="N16" />
</connections>
</pin>
<pin>
<id>M122</id>
<termid>T83</termid>
<connections>
<connection net="N31" />
</connections>
</pin>
<pin>
<id>M123</id>
<termid>T84</termid>
<connections>
<connection net="N19" />
</connections>
</pin>
<pin>
<id>M124</id>
<termid>T85</termid>
<connections>
<connection net="N31" />
</connections>
</pin>
<pin>
<id>M125</id>
<termid>T86</termid>
<connections>
<connection net="N32" />
</connections>
</pin>
<pin>
<id>M126</id>
<termid>T87</termid>
<connections>
<connection net="N31" />
</connections>
</pin>
<pin>
<id>M127</id>
<termid>T88</termid>
<connections>
</connections>
</pin>
<pin>
<id>M128</id>
<termid>T89</termid>
<connections>
<connection net="N31" />
</connections>
</pin>
<pin>
<id>M129</id>
<termid>T90</termid>
<connections>
<connection net="N4" />
</connections>
</pin>
<pin>
<id>M130</id>
<termid>T91</termid>
<connections>
<connection net="N4" />
</connections>
</pin>
<pin>
<id>M131</id>
<termid>T92</termid>
<connections>
<connection net="N4" />
</connections>
</pin>
<pin>
<id>M132</id>
<termid>T93</termid>
<connections>
<connection net="N4" />
</connections>
</pin>
<pin>
<id>M133</id>
<termid>T94</termid>
<connections>
<connection net="N4" />
</connections>
</pin>
<pin>
<id>M134</id>
<termid>T95</termid>
<connections>
<connection net="N4" />
</connections>
</pin>
<pin>
<id>M135</id>
<termid>T96</termid>
<connections>
<connection net="N33" />
</connections>
</pin>
<pin>
<id>M136</id>
<termid>T97</termid>
<connections>
<connection net="N34" />
</connections>
</pin>
<pin>
<id>M137</id>
<termid>T98</termid>
<connections>
<connection net="N36" />
</connections>
</pin>
<pin>
<id>M138</id>
<termid>T99</termid>
<connections>
<connection net="N35" />
</connections>
</pin>
<pin>
<id>M139</id>
<termid>T100</termid>
<connections>
<connection net="N37" />
</connections>
</pin>
<pin>
<id>M140</id>
<termid>T101</termid>
<connections>
</connections>
</pin>
<pin>
<id>M141</id>
<termid>T102</termid>
<connections>
<connection net="N30" />
</connections>
</pin>
<pin>
<id>M142</id>
<termid>T103</termid>
<connections>
</connections>
</pin>
<pin>
<id>M143</id>
<termid>T104</termid>
<connections>
</connections>
</pin>
<pin>
<id>M144</id>
<termid>T105</termid>
<connections>
</connections>
</pin>
<pin>
<id>M145</id>
<termid>T106</termid>
<connections>
<connection net="N31" />
</connections>
</pin>
<pin>
<id>M146</id>
<termid>T107</termid>
<connections>
<connection net="N40" />
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
<instance>
<id>I27</id>
<cellid>S14</cellid>
<name>page1_i31</name>
<parameters>
</parameters>
<masks>
</masks>
<powers>
</powers>
<pins>
<pin>
<id>M147</id>
<termid>T108</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N40" />
</connections>
</pin>
<pin>
<id>M148</id>
<termid>T109</termid>
<msb>0</msb>
<lsb>0</lsb>
<connections>
<connection pinmsb="0" pinlsb="0" net="N4" />
</connections>
</pin>
</pins>
<differentialpins>
</differentialpins>
<differentialbuspins>
</differentialbuspins>
<portgroups>
</portgroups>
<portinterfaces>
</portinterfaces>
</instance>
</instances>
<templateresolutions>
</templateresolutions>
<templateinstances>
</templateinstances>
<extensions>
<extension name="schematic_extension">
<schematicExtension>
<netScopes>
<netScope ref="ecl_to_lvds_in">
<pageScope number="1">
<scope>interface</scope>
<direction>input</direction>
</pageScope>
</netScope>
<netScope ref="ecl_to_nim_in">
<pageScope number="1">
<scope>interface</scope>
<direction>input</direction>
</pageScope>
</netScope>
<netScope ref="ecl_to_nim_out">
<pageScope number="1">
<scope>interface</scope>
<direction>output</direction>
</pageScope>
</netScope>
<netScope ref="ecl_to_ttl_in">
<pageScope number="1">
<scope>interface</scope>
<direction>input</direction>
</pageScope>
</netScope>
<netScope ref="ecl_to_ttl_out">
<pageScope number="1">
<scope>interface</scope>
<direction>output</direction>
</pageScope>
</netScope>
<netScope ref="gnd">
<pageScope number="1">
<scope>global</scope>
</pageScope>
</netScope>
<netScope ref="lvds_to_ecl_out_n">
<pageScope number="1">
<scope>interface</scope>
<direction>output</direction>
</pageScope>
</netScope>
<netScope ref="lvds_to_ecl_out_p">
<pageScope number="1">
<scope>interface</scope>
<direction>output</direction>
</pageScope>
</netScope>
<netScope ref="ttl_to_ecl_in">
<pageScope number="1">
<scope>interface</scope>
<direction>input</direction>
</pageScope>
</netScope>
<netScope ref="ttl_to_ecl_out_n">
<pageScope number="1">
<scope>interface</scope>
<direction>output</direction>
</pageScope>
</netScope>
<netScope ref="ttl_to_ecl_out_p">
<pageScope number="1">
<scope>interface</scope>
<direction>output</direction>
</pageScope>
</netScope>
<netScope ref="vcc">
<pageScope number="1">
<scope>global</scope>
</pageScope>
</netScope>
<netScope ref="vee">
<pageScope number="1">
<scope>global</scope>
</pageScope>
</netScope>
</netScopes>
<pages>
<page number="1">
<physicalPageNumber>1</physicalPageNumber>
<errorStatus>false</errorStatus>
<nets>
<net ref="ecl_to_lvds_in"></net>
<net ref="ecl_to_lvds_out_n"></net>
<net ref="ecl_to_lvds_out_p"></net>
<net ref="ecl_to_nim_in"></net>
<net ref="ecl_to_nim_out"></net>
<net ref="ecl_to_ttl_in"></net>
<net ref="ecl_to_ttl_out"></net>
<net ref="gnd"></net>
<net ref="lvds_to_ecl_in_n"></net>
<net ref="lvds_to_ecl_in_p"></net>
<net ref="lvds_to_ecl_out_n"></net>
<net ref="lvds_to_ecl_out_p"></net>
<net ref="nim_to_ecl_in"></net>
<net ref="nim_to_ecl_out"></net>
<net ref="ttl_to_ecl_in"></net>
<net ref="ttl_to_ecl_out_n"></net>
<net ref="ttl_to_ecl_out_p"></net>
<net ref="unnamed_1_csmd0805_i10_a"></net>
<net ref="unnamed_1_csmd0805_i10_b"></net>
<net ref="unnamed_1_csmd0805_i13_a"></net>
<net ref="unnamed_1_csmd0805_i13_b"></net>
<net ref="unnamed_1_csmd0805_i14_b"></net>
<net ref="unnamed_1_csmd0805_i9_b"></net>
<net ref="unnamed_1_ds90lv019_i15_din"></net>
<net ref="unnamed_1_ds90lv019_i15_rout"></net>
<net ref="unnamed_1_mc10e116_i30_d0"></net>
<net ref="unnamed_1_mc10e116_i30_d3"></net>
<net ref="unnamed_1_mc10e116_i30_q0"></net>
<net ref="unnamed_1_mc10e116_i30_q0_1"></net>
<net ref="unnamed_1_mc10e116_i30_q1"></net>
<net ref="unnamed_1_mc10e116_i30_q1_1"></net>
<net ref="unnamed_1_mc10e116_i30_q2"></net>
<net ref="unnamed_1_mpsh81_i17_c"></net>
<net ref="unnamed_1_rsmd0805_i20_a"></net>
<net ref="vcc"></net>
<net ref="vee"></net>
</nets>
<instances>
<instance ref="i1"></instance>
<instance ref="i2"></instance>
<instance ref="i3"></instance>
<instance ref="i9"></instance>
<instance ref="i10"></instance>
<instance ref="i11"></instance>
<instance ref="i12"></instance>
<instance ref="i13"></instance>
<instance ref="i14"></instance>
<instance ref="i15"></instance>
<instance ref="i16"></instance>
<instance ref="i17"></instance>
<instance ref="i18"></instance>
<instance ref="i20"></instance>
<instance ref="i21"></instance>
<instance ref="i22"></instance>
<instance ref="i23"></instance>
<instance ref="i24"></instance>
<instance ref="i25"></instance>
<instance ref="i26"></instance>
<instance ref="i27"></instance>
<instance ref="i28"></instance>
<instance ref="i29"></instance>
<instance ref="i30"></instance>
<instance ref="i31"></instance>
</instances>
</page>
</pages>
</schematicExtension>
</extension>
</extensions>
</design>
</designs>
</schema>