2493 lines
99 KiB
OpenEdge ABL
2493 lines
99 KiB
OpenEdge ABL
(wiring
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# Wiring file created by Allegro PCB Router v16-6-112 made 2012/09/12 at 23:00:45
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(resolution MIL 100)
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# Net BACKPLANE_IN<1>
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(wire (path BOTTOM 700 860000 1242090 860000 1190000))
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(wire (path TOP 700 860000 1242090 859990 1242100 830750 1242100
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830250 1242600 830250 1245000))
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(via VIA 860000 1242090)
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# Net BACKPLANE_IN<2>
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(wire (path BOTTOM 700 850000 1218600 850000 1190000))
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(wire (path TOP 700 850000 1218600 846400 1218600 835000 1230000
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835000 1231500 831500 1235000 830250 1235000))
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(via VIA 850000 1218600)
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# Net BACKPLANE_IN<3>
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(wire (path BOTTOM 700 840140 1234110 840140 1190140 840000 1190000))
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(wire (path TOP 700 840140 1234110 845510 1234110 846400 1235000
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849750 1235000))
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(via VIA 840140 1234110)
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# Net BACKPLANE_IN<4>
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(wire (path BOTTOM 700 834450 1245000 834450 1194450 830000 1190000))
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(wire (path TOP 700 834450 1245000 849750 1245000))
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(via VIA 834450 1245000)
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# Net BACKPLANE_IN<5>
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(wire (path TOP 700 780250 1245000 783600 1245000 783600 1238240
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782810 1237450 774950 1237450 772500 1235000 772500 1210000
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797250 1185250 854750 1185250 860000 1180000))
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# Net BACKPLANE_IN<6>
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(wire (path BOTTOM 700 787250 1235000 787250 1204850 818750 1173350
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843350 1173350 850000 1180000))
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(wire (path TOP 700 787250 1235000 780250 1235000))
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(via VIA 787250 1235000)
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# Net BACKPLANE_IN<7>
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(wire (path BOTTOM 700 805260 1235000 805260 1189150 818260 1176150
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836150 1176150 840000 1180000))
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(wire (path TOP 700 805260 1235000 799750 1235000))
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(via VIA 805260 1235000)
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# Net BACKPLANE_IN<8>
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(wire (path BOTTOM 700 810000 1245000 813720 1245000 825250 1233470
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825250 1184750 830000 1180000))
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(wire (path TOP 700 810000 1245000 799750 1245000))
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(via VIA 810000 1245000)
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# Net BACKPLANE_IN<9>
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(wire (path BOTTOM 700 814750 1205610 814750 1185250 820000 1180000))
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(wire (path TOP 700 814750 1205610 846200 1205610 865700 1225110
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865700 1231500 876700 1242500 880250 1242500))
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(via VIA 814750 1205610)
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# Net BACKPLANE_IN<10>
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(wire (path TOP 700 899750 1232500 903500 1232500 904500 1231500
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904500 1209510 891640 1196650 826650 1196650 820000 1190000))
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# Net BACKPLANE_OUT<1>
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(wire (path TOP 700 830250 1255000 826550 1255000 826550 1263550))
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(wire (path TOP 700 830250 1255000 834000 1255000 835000 1254000
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835000 1251000 834000 1250000 830250 1250000))
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(wire (path BOTTOM 700 826550 1263550 810000 1280100 810000 1290000))
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(via VIA 826550 1263550)
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# Net BACKPLANE_OUT<2>
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(wire (path TOP 700 825900 1230000 825900 1225790 826690 1225000
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830250 1225000))
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(wire (path TOP 700 825900 1230000 820350 1235550 820350 1289650
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820000 1290000))
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(wire (path TOP 700 825900 1230000 830250 1230000))
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# Net BACKPLANE_OUT<3>
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(wire (path TOP 700 849750 1230000 838500 1230000 837500 1231000
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837500 1235000 835050 1237450 827800 1237450 822710 1242540
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822710 1274750 830000 1282040 830000 1290000))
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(wire (path TOP 700 849750 1230000 849750 1225000))
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# Net BACKPLANE_OUT<4>
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(wire (path TOP 700 846400 1255000 846400 1263340 851590 1268530
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851590 1278410 840000 1290000))
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(wire (path TOP 700 846400 1255000 846400 1250000 849750 1250000))
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(wire (path TOP 700 846400 1255000 849750 1255000))
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# Net BACKPLANE_OUT<5>
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(wire (path TOP 700 785000 1250000 785000 1254000 784000 1255000
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780250 1255000))
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(wire (path TOP 700 785000 1250000 787100 1247900 803400 1247900
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805900 1250400 805900 1295900 810000 1300000))
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(wire (path TOP 700 785000 1250000 780250 1250000))
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# Net BACKPLANE_OUT<6>
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(wire (path BOTTOM 700 791550 1230000 791550 1277250 809550 1295250
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815250 1295250 820000 1300000))
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(wire (path TOP 700 783600 1230000 783600 1225000 780250 1225000))
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(wire (path TOP 700 791550 1230000 783600 1230000))
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(wire (path TOP 700 783600 1230000 780250 1230000))
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(via VIA 791550 1230000)
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# Net BACKPLANE_OUT<7>
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(wire (path TOP 700 796400 1230000 796400 1225000 799750 1225000))
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(wire (path TOP 700 796400 1230000 796400 1241660 797190 1242450
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814200 1242450 815770 1244020 815770 1291250 819770 1295250
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825250 1295250 830000 1300000))
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(wire (path TOP 700 796400 1230000 799750 1230000))
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# Net BACKPLANE_OUT<8>
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(wire (path TOP 700 804500 1255000 804500 1251000 803500 1250000
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799750 1250000))
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(wire (path TOP 700 804500 1255000 804500 1300250 809500 1305250
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834750 1305250 840000 1300000))
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(wire (path TOP 700 804500 1255000 799750 1255000))
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# Net BACKPLANE_OUT<9>
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(wire (path TOP 700 880250 1247500 876550 1247500 869050 1255000
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869050 1263620 846150 1286520 846150 1296150 850000 1300000))
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(wire (path TOP 700 880250 1247500 884000 1247500 885000 1246500
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885000 1238500 884000 1237500 880250 1237500))
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# Net BACKPLANE_OUT<10>
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(wire (path TOP 700 905000 1242500 905900 1243400 905900 1264500
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880400 1290000 850000 1290000))
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(wire (path TOP 700 905000 1242500 899750 1242500))
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(wire (path TOP 700 905000 1242500 905000 1241500 901000 1237500
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899750 1237500))
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# Net BCKP_CLK*
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(wire (path TOP 700 870050 520050 845000 495000 845000 447000))
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# Net BCKP_CLK_BUFD_N
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# Net BCKP_CLK_BUFD_P
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# Net CAEN_BUFF_CNTRL<0>
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# Net CAEN_BUFF_CNTRL<1>
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# Net CAEN_BUFF_CNTRL<2>
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# Net CAEN_BUFF_CNTRL<3>
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# Net CAEN_BUFF_CNTRL<4>
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# Net CAEN_BUFF_CNTRL<5>
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# Net CAEN_BUFF_CNTRL<6>
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# Net CAEN_BUFF_CNTRL<7>
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# Net CHANGE_CLK2_N
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# Net CHANGE_CLK2_P
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# Net CHOSEN_CLK2_N
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# Net CHOSEN_CLK2_P
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# Net CHOSEN_CLK_N
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# Net CHOSEN_CLK_P
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# Net CLK_BAD_N
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# Net CLK_BAD_P
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# Net CLK_MISSED
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# Net CLK_SEL_ECL_N
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(wire (path BOTTOM 700 860000 440000 839710 440000))
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(wire (path TOP 700 870190 460000 876060 460000))
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(wire (path TOP 700 836350 440000 836350 443500 775000 443500
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775000 447000))
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(wire (path TOP 700 839710 440000 836350 440000))
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(wire (path TOP 700 836350 440000 833000 440000))
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(wire (path BOTTOM 700 860000 440000 870190 450190 870190 460000))
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(wire (path TOP 700 860000 440000 860000 447000))
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(via VIA 839710 440000)
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(via VIA 870190 460000)
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(via VIA 860000 440000)
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# Net CLK_SEL_ECL_P
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(wire (path TOP 700 863650 425000 863650 427100 870350 427100
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870350 435000 867000 435000))
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(wire (path TOP 700 863650 425000 863650 422900 876450 422900
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876450 426060 880000 426060))
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(wire (path TOP 700 844110 425000 863650 425000))
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(wire (path TOP 700 833000 425000 840010 425000))
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(wire (path TOP 700 833000 425000 811350 425000 811350 440000
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787000 440000))
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(wire (path BOTTOM 700 840010 425000 844110 425000))
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(via VIA 844110 425000)
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(via VIA 840010 425000)
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# Net CLK_STATE
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# Net CNTRL_RAW<0>
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(wire (path BOTTOM 700 305000 1330000 305000 1325000 307050 1325000))
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(wire (path BOTTOM 700 300000 1272400 307050 1272400 307050 1325000))
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(wire (path BOTTOM 700 331950 1325000 307050 1325000))
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(wire (path TOP 700 305000 1330000 301150 1330000 301150 1326160
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293800 1326160))
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(wire (path TOP 700 331950 1325000 347250 1325000))
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(wire (path TOP 700 300000 1272400 300000 1280000))
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(via VIA 300000 1272400)
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(via VIA 331950 1325000)
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# Net CNTRL_RAW<1>
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(wire (path TOP 700 298750 1285250 295000 1285250 295000 1280000))
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(wire (path TOP 700 337500 1280000 337500 1274750 367750 1274750
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367750 1330000 347250 1330000))
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(wire (path TOP 700 337500 1280000 337500 1285250 298750 1285250))
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(wire (path BOTTOM 700 298750 1328720 298750 1285250))
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(wire (path TOP 700 298750 1328720 293800 1328720))
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(via VIA 298750 1285250)
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(via VIA 298750 1328720)
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# Net CNTRL_RAW<2>
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(wire (path TOP 700 305000 1355000 354800 1355000 354800 1335000
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347250 1335000))
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(wire (path BOTTOM 700 305000 1355000 305000 1336400 290000 1336400
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290000 1331280))
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(wire (path BOTTOM 700 290000 1284200 290000 1331280))
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(wire (path BOTTOM 700 287100 1331280 290000 1331280))
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(wire (path TOP 700 287100 1331280 293800 1331280))
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(wire (path TOP 700 290000 1284200 290000 1280000))
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(via VIA 287100 1331280)
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(via VIA 290000 1284200)
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# Net CNTRL_RAW<3>
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(wire (path TOP 700 280000 1355000 280000 1348500 350600 1348500
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350600 1340000 347250 1340000))
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(wire (path BOTTOM 700 280000 1355000 280000 1333840 285000 1333840))
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(wire (path TOP 700 285000 1284200 285000 1280000))
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(wire (path BOTTOM 700 285000 1284200 285000 1333840))
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(wire (path TOP 700 285000 1333840 293800 1333840))
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(via VIA 285000 1333840)
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(via VIA 285000 1284200)
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# Net CNTRL_RAW<4>
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(wire (path TOP 700 280000 1284200 280000 1280000))
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(wire (path BOTTOM 700 255000 1330000 255000 1284200 277950 1284200))
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(wire (path BOTTOM 700 318450 1335000 300800 1335000 300800 1280750
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277950 1280750 277950 1284200))
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(wire (path BOTTOM 700 280000 1284200 277950 1284200))
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(wire (path TOP 700 255000 1330000 258850 1330000 258850 1333840
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266200 1333840))
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(wire (path TOP 700 318450 1335000 327750 1335000))
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(via VIA 280000 1284200)
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(via VIA 318450 1335000)
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# Net CNTRL_RAW<5>
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(wire (path TOP 700 282050 1331280 282050 1318140 319000 1318140
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319000 1330000 327750 1330000))
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(wire (path TOP 700 266200 1331280 260250 1331280 260250 1326150
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249750 1326150 249750 1355000 255000 1355000))
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(wire (path TOP 700 266200 1331280 282050 1331280))
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(wire (path TOP 700 282050 1288500 275000 1288500 275000 1280000))
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(wire (path BOTTOM 700 282050 1288500 282050 1331280))
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(via VIA 282050 1331280)
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(via VIA 282050 1288500)
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# Net CNTRL_RAW<6>
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(wire (path BOTTOM 700 362500 1322900 362500 1305000))
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(wire (path TOP 700 362500 1322900 324400 1322900 324400 1325000
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327750 1325000))
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(wire (path BOTTOM 700 270000 1294650 270000 1328720 272350 1328720))
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(wire (path TOP 700 270000 1294650 270000 1280000))
|
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(wire (path BOTTOM 700 362500 1322900 362500 1360250 272350 1360250
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272350 1328720))
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(wire (path TOP 700 272350 1328720 266200 1328720))
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(via VIA 272350 1328720)
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(via VIA 270000 1294650)
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(via VIA 362500 1322900)
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# Net CNTRL_RAW<7>
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(wire (path TOP 700 270300 1309950 331100 1309950))
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(wire (path TOP 700 270300 1309950 265000 1309950 265000 1280000))
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(wire (path TOP 700 270300 1309950 270300 1326160 266200 1326160))
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(wire (path TOP 700 331100 1309950 331100 1293650 362500 1293650
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362500 1280000))
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(wire (path TOP 700 331100 1309950 331100 1320000 327750 1320000))
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# Net COMP1_THRESH
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# Net COMP2_THRESH
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# Net COUNT
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# Net COUNT_DATA_ECL<0>
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# Net COUNT_DATA_ECL<1>
|
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# Net COUNT_DATA_ECL<2>
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# Net COUNT_DATA_ECL<3>
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# Net COUNT_DATA_ECL<4>
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# Net COUNT_DATA_ECL<5>
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# Net COUNT_DATA_ECL<6>
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# Net COUNT_DATA_ECL<7>
|
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# Net DDGT_BITS
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(wire (path TOP 700 1127500 1267500 1127500 1259750))
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(wire (path TOP 700 1137500 1312500 1137500 1319750))
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(wire (path BOTTOM 700 1137500 1312500 1137500 1277500 1127500 1267500))
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(via VIA 1127500 1267500)
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(via VIA 1137500 1312500)
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# Net DDGT_TTL
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(wire (path TOP 700 1191750 1240000 1172500 1240000 1165000 1232500
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1115000 1232500 1112500 1235000 1112500 1240250))
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(wire (path TOP 700 1191750 1240000 1193000 1240000))
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(wire (path TOP 700 1191750 1240000 1189890 1241860 1189890 1242890
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1190000 1243000 1190000 1300250))
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# Net DEF_CLK_DIV2_N
|
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# Net DEF_CLK_DIV2_P
|
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# Net DEF_CLK_DIV4_N
|
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# Net DEF_CLK_DIV4_P
|
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# Net DEF_CLK_DIV8_N
|
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# Net DEF_CLK_DIV8_P
|
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# Net DEF_CLK_DIVD_N
|
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# Net DEF_CLK_DIVD_P
|
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# Net DGT_GATE
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(wire (path TOP 700 1117200 475000 1113000 475000)
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(attr fanout))
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(wire (path TOP 700 1117200 475000 1117200 473910 1116000 472710
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1105000 472710 1105000 476060))
|
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(wire (path TOP 700 1142800 485000 1147000 485000)
|
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(attr fanout))
|
|
(wire (path TOP 700 1131540 490000 1117200 490000))
|
|
(wire (path TOP 700 1117200 490000 1113000 490000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1131540 490000 1137200 490000 1140000 492800
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1140000 497000))
|
|
(wire (path BOTTOM 700 1131540 490000 1136540 485000 1142800 485000))
|
|
(wire (path BOTTOM 700 1117200 490000 1119250 487950 1119250 477050
|
|
1117200 475000))
|
|
(via VIA 1117200 475000
|
|
(attr fanout))
|
|
(via VIA 1117200 490000
|
|
(attr fanout))
|
|
(via VIA 1142800 485000
|
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(attr fanout))
|
|
(via VIA 1131540 490000)
|
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# Net DGT_TTL
|
|
(wire (path TOP 700 1205000 1247000 1205000 1240000 1207500 1237500
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|
1207500 1225000 1202500 1220000 1193000 1220000))
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|
(wire (path TOP 700 1205000 1247000 1205000 1255000 1197290 1262710
|
|
1196940 1262710 1192500 1267150 1192500 1275000 1197500 1280000
|
|
1197500 1307500 1206400 1316400 1211610 1316400 1211850 1316640
|
|
1213140 1316640 1215000 1318500))
|
|
(wire (path TOP 700 1215000 1312500 1215000 1318500))
|
|
(wire (path BOTTOM 700 1142500 1292500 1157500 1292500 1177500 1312500
|
|
1215000 1312500))
|
|
(wire (path TOP 700 1142500 1292500 1142500 1300250))
|
|
(wire (path TOP 700 1215000 1318500 1215000 1319750))
|
|
(via VIA 1215000 1312500)
|
|
(via VIA 1142500 1292500)
|
|
# Net DIVD_CLK_TTL
|
|
# Net ECAL_ACTIVE_ECL_N
|
|
(wire (path TOP 700 410350 1000000 417500 1007150 417500 1052500
|
|
415000 1055000 407000 1055000))
|
|
(wire (path TOP 700 410350 1000000 407000 1000000))
|
|
(wire (path TOP 700 410350 1000000 430000 1000000 430000 996440))
|
|
# Net ECAL_ACTIVE_ECL_P
|
|
(wire (path TOP 700 402110 986200 403310 985000 407000 985000))
|
|
(wire (path BOTTOM 700 402110 982500 393940 982500))
|
|
(wire (path TOP 700 402110 986200 402110 1039640 400000 1041750
|
|
400000 1043000))
|
|
(wire (path TOP 700 402110 982500 402110 986200))
|
|
(via VIA 402110 982500)
|
|
# Net EN_CLK_DIV_ECL
|
|
(wire (path TOP 700 772710 460000 766900 465810 766900 477500
|
|
770250 477500))
|
|
(wire (path TOP 700 772710 460000 776060 460000))
|
|
(wire (path TOP 700 772710 460000 772710 437100 790350 437100
|
|
790350 432100 783650 432100 783650 420000 787000 420000))
|
|
# Net FOX_100MHZ_P
|
|
(wire (path TOP 700 840000 447000 840000 443650 857100 443650
|
|
857100 450450 867290 450450))
|
|
(wire (path TOP 700 867290 450450 867290 460000 863940 460000))
|
|
(wire (path TOP 700 867290 450450 873150 444590 873150 425000
|
|
867000 425000))
|
|
(wire (path TOP 700 840000 447000 840000 472500 789750 472500))
|
|
# Net FOX_CLK_LVPECL_N
|
|
(wire (path TOP 700 733270 540000 798250 540000 798250 549600
|
|
768250 549600 768250 552500 756500 552500))
|
|
# Net FOX_CLK_LVPECL_P
|
|
(wire (path TOP 700 733270 550000 738980 550000 740860 551880
|
|
740860 557500 756500 557500))
|
|
# Net FUZZD_CLK_N
|
|
# Net FUZZD_CLK_P
|
|
# Net GND
|
|
(wire (path TOP 700 205000 95000 200150 99850 200150 138690
|
|
205000 138690 205000 133940))
|
|
(wire (path TOP 700 326060 255000 321310 255000 321310 246250
|
|
339060 246250 339060 242400))
|
|
(wire (path TOP 700 1122500 1247500 1122500 1240250)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1185000 1295000 1185000 1300250)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1220000 1325000 1220000 1319750)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1185000 1319750 1177250 1319750 1172500 1315000
|
|
1172500 1310100)
|
|
(attr fanout))
|
|
(wire (path TOP 700 540000 520000 538940 521060 530000 521060)
|
|
(attr fanout))
|
|
(wire (path TOP 700 409750 415250 409750 420000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1097500 1260000 1097500 1255100)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1162400 844900 1157500 844900)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1205000 810250 1205000 800380 1198560 793940
|
|
1195000 793940)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1215000 810250 1220250 810250 1225000 815000
|
|
1225000 817400)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1097500 1317500 1097500 1312600)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1210000 1307500 1210000 1300250)
|
|
(attr fanout))
|
|
(wire (path TOP 700 393560 407500 393560 413940 390250 417250
|
|
390250 420000))
|
|
(wire (path TOP 700 393560 407500 387500 407500)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 333560 440000 330000 440000 327500 437500))
|
|
(wire (path BOTTOM 700 333560 440000 333560 425000))
|
|
(wire (path TOP 700 327500 437500 320500 437500))
|
|
(wire (path TOP 700 1108000 445000 1111350 445000 1111350 452650))
|
|
(wire (path TOP 700 1108000 445000 1104650 445000 1104650 430000
|
|
1108000 430000))
|
|
(wire (path BOTTOM 700 1255000 480000 1216950 480000 1197500 499450))
|
|
(wire (path TOP 700 1197500 499450 1197500 501500))
|
|
(wire (path TOP 700 1197500 499450 1197500 495250)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1197500 501500 1197500 514750))
|
|
(wire (path TOP 700 1162500 499450 1182450 499450 1182450 501500
|
|
1197500 501500))
|
|
(wire (path TOP 700 1162500 499450 1162500 495250)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1042800 535000 1047000 535000)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1061350 557400 1051050 557400 1040750 547100
|
|
1040750 525000))
|
|
(wire (path BOTTOM 700 1035000 492800 1035000 505600 1040750 511350
|
|
1040750 525000))
|
|
(wire (path BOTTOM 700 1042800 525000 1040750 525000))
|
|
(wire (path TOP 700 1022100 477100 1022100 459860 1020000 457760
|
|
1020000 455000))
|
|
(wire (path TOP 700 1040000 400950 1040000 405000))
|
|
(wire (path TOP 700 1072710 409650 1085000 409650 1085000 413000))
|
|
(wire (path TOP 700 1072710 409650 1072710 416000 1073910 417200
|
|
1075000 417200 1075000 413000))
|
|
(wire (path TOP 700 1040000 400950 1047610 393340 1056400 393340
|
|
1072710 409650))
|
|
(wire (path TOP 700 1022100 477100 1009990 477100 1008250 475360
|
|
1008250 408890 1016190 400950 1040000 400950))
|
|
(wire (path TOP 700 1022100 477100 1022100 489900 1025000 492800))
|
|
(wire (path TOP 700 1035000 492800 1035000 497000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1035000 492800 1025000 492800))
|
|
(wire (path TOP 700 1025000 492800 1025000 497000))
|
|
(wire (path TOP 700 1061350 557400 1061350 560200 1040000 560200))
|
|
(wire (path BOTTOM 700 1042800 525000 1042800 535000))
|
|
(wire (path TOP 700 1097800 515000 1098650 514150 1098650 512200))
|
|
(wire (path TOP 700 1047000 525000 1052100 525000 1053800 523300
|
|
1053800 515000 1058000 515000))
|
|
(wire (path TOP 700 1047000 525000 1042800 525000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1087900 512200 1085000 512200 1085000 508000))
|
|
(wire (path TOP 700 1087900 512200 1087900 479900 1092800 475000
|
|
1097000 475000))
|
|
(wire (path TOP 700 1098650 512200 1087900 512200))
|
|
(wire (path TOP 700 1125000 492800 1109330 492800 1098650 503480
|
|
1098650 512200))
|
|
(wire (path BOTTOM 700 1125000 467200 1125000 492800))
|
|
(wire (path TOP 700 1058000 515000 1097800 515000))
|
|
(wire (path TOP 700 1113000 525000 1102000 525000))
|
|
(wire (path TOP 700 1102000 525000 1097800 525000))
|
|
(wire (path TOP 700 1113000 525000 1117200 525000)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1097800 525000 1097800 515000))
|
|
(wire (path BOTTOM 700 1117200 525000 1117200 535000))
|
|
(wire (path TOP 700 1117200 535000 1113000 535000)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1135000 467200 1137050 469250 1137050 474000
|
|
1162500 499450))
|
|
(wire (path TOP 700 1135000 467200 1135000 463000)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1125000 467200 1135000 467200))
|
|
(wire (path TOP 700 1125000 463000 1125000 459540 1097790 459540))
|
|
(wire (path TOP 700 1125000 463000 1125000 467200)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1097790 459540 1104680 452650 1111350 452650))
|
|
(wire (path TOP 700 1125000 447800 1125000 452000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1147800 440000 1140000 447800))
|
|
(wire (path TOP 700 1147800 440000 1152000 440000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1125000 447800 1140000 447800))
|
|
(wire (path TOP 700 1140000 447800 1140000 452000))
|
|
(wire (path BOTTOM 700 1147800 425000 1147800 440000))
|
|
(wire (path TOP 700 1147800 425000 1152000 425000)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1125000 447800 1120150 452650 1111350 452650))
|
|
(wire (path TOP 700 1195000 1325510 1195000 1319750)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1195000 1325510 1194490 1325510 1190000 1330000
|
|
1190000 1346060)
|
|
(attr fanout))
|
|
(wire (path TOP 700 465000 525000 458000 525000))
|
|
(wire (path TOP 700 465000 510000 458000 510000))
|
|
(wire (path BOTTOM 700 465000 510000 465000 525000))
|
|
(wire (path TOP 700 485000 505000 485000 498000))
|
|
(wire (path BOTTOM 700 485000 505000 470000 505000))
|
|
(wire (path BOTTOM 700 495000 520000 487500 512500 482600 512500))
|
|
(wire (path BOTTOM 700 465000 510000 470000 505000))
|
|
(wire (path TOP 700 470000 505000 470000 498000))
|
|
(wire (path BOTTOM 700 485000 505000 495000 505000))
|
|
(wire (path TOP 700 495000 505000 502000 505000))
|
|
(wire (path BOTTOM 700 495000 505000 495000 520000))
|
|
(wire (path TOP 700 495000 520000 502000 520000))
|
|
(wire (path TOP 700 362390 526060 350000 526060))
|
|
(wire (path TOP 700 362390 526060 365000 526060))
|
|
(wire (path TOP 700 362390 526060 361690 525360 361690 509010
|
|
363200 507500 394300 507500 395000 506800 395000 503000))
|
|
(wire (path TOP 700 845000 416360 855000 416360 855000 413000))
|
|
(wire (path TOP 700 728480 545600 724080 550000 716730 550000))
|
|
(wire (path TOP 700 752100 549600 752100 550000 750000 550000))
|
|
(wire (path TOP 700 842060 422100 842060 442050 837750 442050
|
|
837750 466350 787920 466350 781770 472500))
|
|
(wire (path TOP 700 749650 420000 722600 420000))
|
|
(wire (path TOP 700 788140 530000 850000 530000))
|
|
(wire (path TOP 700 728480 545600 728480 534600 786040 534600
|
|
788140 532500))
|
|
(wire (path TOP 700 781770 472500 781770 480400))
|
|
(wire (path TOP 700 781770 472500 770250 472500))
|
|
(wire (path TOP 700 781770 480400 766900 480400 766900 499600
|
|
785000 499600))
|
|
(wire (path TOP 700 781770 480400 783870 482500 789750 482500))
|
|
(wire (path TOP 700 788140 530000 785000 526860 785000 499600))
|
|
(wire (path TOP 700 785000 499600 785000 497500 789750 497500))
|
|
(wire (path TOP 700 728480 545600 752100 545600 752100 549600))
|
|
(wire (path TOP 700 752100 549600 764050 549600 764050 547500
|
|
793500 547500))
|
|
(wire (path TOP 700 842060 422100 790350 422100))
|
|
(wire (path TOP 700 790350 422100 790350 425000 787000 425000))
|
|
(wire (path TOP 700 788140 530000 788140 532500))
|
|
(wire (path TOP 700 788140 532500 793500 532500))
|
|
(wire (path TOP 700 845000 416360 845000 419160 842060 422100))
|
|
(wire (path TOP 700 845000 416360 845000 413000))
|
|
(wire (path TOP 700 749650 420000 749650 408250 790350 408250
|
|
790350 422100))
|
|
(wire (path TOP 700 749650 420000 753000 420000))
|
|
(wire (path TOP 700 557450 545050 551000 545050)
|
|
(attr fanout))
|
|
(via VIA 1122500 1247500
|
|
(attr fanout))
|
|
(via VIA 1185000 1295000
|
|
(attr fanout))
|
|
(via VIA 1220000 1325000
|
|
(attr fanout))
|
|
(via VIA 540000 520000
|
|
(attr fanout))
|
|
(via VIA 409750 415250
|
|
(attr fanout))
|
|
(via VIA 1097500 1260000
|
|
(attr fanout))
|
|
(via VIA 1162400 844900
|
|
(attr fanout))
|
|
(via VIA 1097500 1317500
|
|
(attr fanout))
|
|
(via VIA 1210000 1307500
|
|
(attr fanout))
|
|
(via VIA 387500 407500
|
|
(attr fanout))
|
|
(via VIA 327500 437500)
|
|
(via VIA 1111350 452650)
|
|
(via VIA 1197500 499450
|
|
(attr fanout))
|
|
(via VIA 1162500 499450
|
|
(attr fanout))
|
|
(via VIA 1042800 535000
|
|
(attr fanout))
|
|
(via VIA 1035000 492800
|
|
(attr fanout))
|
|
(via VIA 1061350 557400)
|
|
(via VIA 1042800 525000
|
|
(attr fanout))
|
|
(via VIA 1125000 492800)
|
|
(via VIA 1097800 515000)
|
|
(via VIA 1117200 535000
|
|
(attr fanout))
|
|
(via VIA 1097800 525000)
|
|
(via VIA 1117200 525000
|
|
(attr fanout))
|
|
(via VIA 1135000 467200
|
|
(attr fanout))
|
|
(via VIA 1125000 467200
|
|
(attr fanout))
|
|
(via VIA 1097790 459540)
|
|
(via VIA 1125000 447800
|
|
(attr fanout))
|
|
(via VIA 1147800 440000
|
|
(attr fanout))
|
|
(via VIA 1147800 425000
|
|
(attr fanout))
|
|
(via VIA 465000 525000)
|
|
(via VIA 495000 520000)
|
|
(via VIA 495000 505000)
|
|
(via VIA 470000 505000)
|
|
(via VIA 465000 510000)
|
|
(via VIA 485000 505000)
|
|
(via VIA 557450 545050
|
|
(attr fanout))
|
|
# Net GNG
|
|
# Net GT2_N
|
|
(wire (path TOP 700 535000 852000 535000 865000 520000 880000)
|
|
(net GT2_N )
|
|
(attr fanout))
|
|
# Net GT_2
|
|
(wire (path TOP 700 567500 807500 567500 822500 565000 825000
|
|
552000 825000))
|
|
(wire (path TOP 700 533750 778500 545000 778500 545040 778540
|
|
546040 778540 547500 780000))
|
|
(wire (path BOTTOM 700 547500 780000 567500 800000 567500 807500))
|
|
(wire (path TOP 700 533750 778500 533750 780360 533560 780550
|
|
533560 790000))
|
|
(via VIA 567500 807500)
|
|
(via VIA 547500 780000)
|
|
# Net LE_CAEN
|
|
# Net LE_CLKS
|
|
# Net LE_CNTRL_REG
|
|
# Net LE_GEN_UTILS
|
|
(wire (path BOTTOM 700 1145000 820000 1140000 825000 1120000 825000))
|
|
(wire (path TOP 700 1145000 820000 1145000 807250))
|
|
(wire (path TOP 700 1120000 825000 1120000 840250))
|
|
(via VIA 1120000 825000)
|
|
(via VIA 1145000 820000)
|
|
# Net LE_GT_DELAYS
|
|
(wire (path TOP 700 1142500 1259750 1142500 1261000 1140000 1263500
|
|
1140000 1310000 1142500 1312500 1142500 1319750))
|
|
# Net LE_MTCA_MIMIC
|
|
# Net LO_SEL_ECL_N
|
|
(wire (path TOP 700 852500 1003560 848940 1003560 837880 992500
|
|
818250 992500 815000 995750 815000 997000))
|
|
(wire (path TOP 700 852500 1003560 874690 1003560 880000 998250
|
|
880000 997000))
|
|
# Net LO_SEL_ECL_P
|
|
(wire (path TOP 700 895000 997000 895000 995750 891750 992500
|
|
877500 992500 872500 997500 847500 997500 840000 990000
|
|
827000 990000))
|
|
(wire (path TOP 700 895000 997000 895000 1002500))
|
|
(wire (path BOTTOM 700 895000 1002500 918740 1002500 927300 993940
|
|
927500 993940))
|
|
(via VIA 895000 1002500)
|
|
# Net LO_STAR_RAW
|
|
(wire (path TOP 700 900000 997000 903000 997000 907500 992500
|
|
907500 990500 907000 990000))
|
|
(wire (path TOP 700 875000 1028000 875000 1026750 884250 1017500
|
|
892500 1017500 900000 1010000 900000 997000))
|
|
(wire (path TOP 700 875000 1028000 875000 1035000))
|
|
(wire (path BOTTOM 700 875000 1035000 862500 1035000 860000 1037500
|
|
860000 1060000))
|
|
(wire (path TOP 700 868000 1060000 869250 1060000 871110 1058140
|
|
871110 1056890 880500 1047500 885000 1047500))
|
|
(wire (path TOP 700 860000 1060000 868000 1060000))
|
|
(wire (path BOTTOM 700 885000 1047500 886060 1046440 886060 1040000))
|
|
(via VIA 860000 1060000)
|
|
(via VIA 875000 1035000)
|
|
(via VIA 885000 1047500)
|
|
# Net LOAD_COUNT*
|
|
# Net NEG_TRIG1
|
|
(wire (path TOP 700 1120000 513000 1120000 517200 1125700 522900
|
|
1150350 522900 1150350 532100 1064300 532100 1062200 530000))
|
|
(wire (path TOP 700 1120000 513000 1120000 509650 1137880 509650
|
|
1142100 505430))
|
|
(wire (path TOP 700 1142100 505430 1142100 510690 1151100 510690
|
|
1151100 497710 1159950 497710 1159950 501810 1163160 501810
|
|
1163160 505370 1181800 505370 1184700 508270 1184700 516950
|
|
1185850 518100 1201450 518100 1201450 497710 1230000 497710
|
|
1230000 501060))
|
|
(wire (path TOP 700 1142100 505430 1142100 490000 1147000 490000))
|
|
(wire (path TOP 700 1062200 530000 1058000 530000)
|
|
(attr fanout))
|
|
(via VIA 1062200 530000
|
|
(attr fanout))
|
|
# Net NEG_TRIG2
|
|
(wire (path TOP 700 1065000 547800 1065000 552000)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1108800 540010 1106750 542060 1058750 542060
|
|
1058750 544930 1061620 547800 1065000 547800))
|
|
(wire (path BOTTOM 700 1117200 485000 1113750 481550 1113750 469250
|
|
1117850 465150 1193060 465150))
|
|
(wire (path TOP 700 1108800 540010 1113000 540010 1113000 540000))
|
|
(wire (path TOP 700 1193060 465150 1193060 430550 1202300 421310
|
|
1230000 421310 1230000 426060))
|
|
(wire (path BOTTOM 700 1117200 485000 1108800 493400 1108800 540010))
|
|
(wire (path TOP 700 1117200 485000 1113000 485000)
|
|
(attr fanout))
|
|
(via VIA 1065000 547800
|
|
(attr fanout))
|
|
(via VIA 1193060 465150)
|
|
(via VIA 1108800 540010)
|
|
(via VIA 1117200 485000
|
|
(attr fanout))
|
|
# Net Orphan_net
|
|
(wire (path TOP 700 790150 1127150 792500 1127150)
|
|
(net Orphan_net )
|
|
(type route))
|
|
(wire (path TOP 700 400000 1077000 400000 1080360 409640 1090000)
|
|
(net Orphan_net )
|
|
(type route))
|
|
# Net POS_TRIG1
|
|
(wire (path TOP 700 1062200 525000 1058000 525000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1117200 520000 1113000 520000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1117200 520000 1117200 520900 1116000 522100
|
|
1065100 522100 1062200 525000))
|
|
(wire (path TOP 700 1228360 521790 1228800 521790 1230000 522990
|
|
1230000 526060))
|
|
(wire (path BOTTOM 700 1122950 475000 1122950 508150))
|
|
(wire (path BOTTOM 700 1228360 521790 1225660 519090 1157320 519090
|
|
1155300 517070 1155300 502950 1128150 502950 1122950 508150))
|
|
(wire (path BOTTOM 700 1117200 520000 1122050 515150 1122050 509050
|
|
1122950 508150))
|
|
(wire (path TOP 700 1122950 475000 1147000 475000))
|
|
(via VIA 1062200 525000
|
|
(attr fanout))
|
|
(via VIA 1117200 520000
|
|
(attr fanout))
|
|
(via VIA 1228360 521790)
|
|
(via VIA 1122950 475000)
|
|
# Net POS_TRIG2
|
|
(wire (path TOP 700 1120000 501200 1120000 497000)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1062200 545000 1115150 545000))
|
|
(wire (path BOTTOM 700 1120000 501200 1115150 506050 1115150 545000))
|
|
(wire (path BOTTOM 700 1255000 545000 1115150 545000))
|
|
(wire (path TOP 700 1255000 545000 1255000 551060))
|
|
(wire (path TOP 700 1062200 545000 1058000 545000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1062200 545000 1064400 542800 1120000 542800
|
|
1120000 547000))
|
|
(via VIA 1120000 501200
|
|
(attr fanout))
|
|
(via VIA 1255000 545000)
|
|
(via VIA 1062200 545000
|
|
(attr fanout))
|
|
# Net PREP_RETRIG1
|
|
(wire (path TOP 700 1011780 548030 1013180 548030 1017200 544010
|
|
1017200 540000 1013000 540000))
|
|
(wire (path TOP 700 1011780 548030 1011780 563750 1017030 569000
|
|
1178710 569000 1189360 558350 1189360 547710 1205000 547710
|
|
1205000 551060))
|
|
(wire (path TOP 700 1011780 548030 1006200 548030 1006200 515000
|
|
1020000 501200 1020000 497000))
|
|
# Net PREP_RETRIG2
|
|
(wire (path TOP 700 1013000 520000 1009650 523350 1009650 527100
|
|
1137040 527100))
|
|
(wire (path TOP 700 1013000 520000 1017200 520000)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1147450 505000 1147450 527100 1137040 527100))
|
|
(wire (path TOP 700 1147450 505000 1147450 494900 1154070 494900
|
|
1165360 483610 1169910 483610 1173690 479830 1173690 476060
|
|
1180000 476060))
|
|
(wire (path TOP 700 1040000 501200 1040000 497000)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1040000 501200 1040000 493370 1037380 490750
|
|
1022900 490750 1017200 496450 1017200 520000))
|
|
(via VIA 1017200 520000
|
|
(attr fanout))
|
|
(via VIA 1137040 527100)
|
|
(via VIA 1147450 505000)
|
|
(via VIA 1040000 501200
|
|
(attr fanout))
|
|
# Net RESET_CLK_DIV_ECL
|
|
(wire (path TOP 700 776500 555400 828690 555400 828690 560000
|
|
823940 560000))
|
|
(wire (path TOP 700 770250 502500 776500 502500))
|
|
(wire (path TOP 700 770250 502500 762900 502500 762900 435000
|
|
787000 435000))
|
|
(wire (path BOTTOM 700 776500 502500 776500 555400))
|
|
(via VIA 776500 555400)
|
|
(via VIA 776500 502500)
|
|
# Net RESTART_COUNT
|
|
# Net RETRIG_GATE1
|
|
(wire (path TOP 700 1062200 520000 1058000 520000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1042800 540000 1047000 540000)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1044850 508730 1050930 508730))
|
|
(wire (path BOTTOM 700 1055000 396790 1050930 400860 1050930 508730))
|
|
(wire (path BOTTOM 700 1062200 520000 1050930 508730))
|
|
(wire (path TOP 700 1055000 396790 1055000 401060))
|
|
(wire (path TOP 700 1044850 517050 1044850 508730))
|
|
(wire (path BOTTOM 700 1044850 517050 1044850 537950 1042800 540000))
|
|
(via VIA 1062200 520000
|
|
(attr fanout))
|
|
(via VIA 1042800 540000
|
|
(attr fanout))
|
|
(via VIA 1044850 508730)
|
|
(via VIA 1055000 396790)
|
|
(via VIA 1044850 517050)
|
|
# Net RETRIG_GATE2
|
|
(wire (path TOP 700 1058000 540000 1053800 540000 1053800 547650))
|
|
(wire (path TOP 700 1058000 540000 1062200 540000)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1194410 554650 1060800 554650 1053800 547650))
|
|
(wire (path TOP 700 1194410 554650 1194410 558470 1198230 562290
|
|
1233810 562290 1233810 545230 1224000 535420 1224000 526060
|
|
1205000 526060))
|
|
(wire (path TOP 700 1051640 520000 1047000 520000))
|
|
(wire (path BOTTOM 700 1051640 520000 1051640 529440 1062200 540000))
|
|
(via VIA 1062200 540000
|
|
(attr fanout))
|
|
(via VIA 1053800 547650)
|
|
(via VIA 1194410 554650)
|
|
(via VIA 1051640 520000)
|
|
# Net RIB1_N
|
|
(wire (path TOP 700 1250000 993000 1250000 991750 1238250 980000
|
|
1230000 980000 1204050 1005950 1204050 1028390 1180700 1051740
|
|
1180700 1060000 1180000 1060000))
|
|
# Net RIB1_P
|
|
(wire (path TOP 700 1257000 1000000 1257000 995040 1239460 977500
|
|
1230000 977500 1202650 1004850 1202650 1027810 1179300 1051160
|
|
1179300 1055250 1176150 1058400 1176150 1061600 1180000 1065450
|
|
1180000 1070000))
|
|
# Net RIB2_N
|
|
(wire (path TOP 700 1175000 1027000 1175000 1022490)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1192570 1005210 1195850 1005210 1195850 1004830
|
|
1195980 1004700 1204790 1004700 1204790 975300 1215250 964840
|
|
1215250 960740 1215990 960000 1220000 960000))
|
|
(wire (path TOP 700 1192060 1015460 1192060 1012180 1192440 1012180
|
|
1193080 1011540 1193080 1007260 1192570 1007260 1192570 1005210))
|
|
(wire (path TOP 700 1192060 1020760 1192060 1015460))
|
|
(wire (path BOTTOM 700 1176060 1040000 1170700 1040000 1170700 1043810
|
|
1190370 1043810 1196540 1037640 1196540 1018500 1194110 1016070
|
|
1194110 1015460 1192060 1015460))
|
|
(wire (path BOTTOM 700 1175000 1022490 1176450 1021040 1177200 1021790
|
|
1190010 1021790 1190010 1020760 1192060 1020760))
|
|
(via VIA 1175000 1022490
|
|
(attr fanout))
|
|
(via VIA 1192570 1005210)
|
|
(via VIA 1192060 1020760)
|
|
(via VIA 1192060 1015460)
|
|
# Net RIB2_P
|
|
(wire (path TOP 700 1165000 1027000 1165000 1022490)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1195000 1002780 1197050 1002780 1197050 1003300
|
|
1203390 1003300 1203390 974720 1213850 964260 1213850 960160
|
|
1220000 954010 1220000 950000))
|
|
(wire (path TOP 700 1194490 1013030 1194490 1010980 1194480 1010980
|
|
1194480 1006200 1195000 1005680 1195000 1002780))
|
|
(wire (path TOP 700 1194490 1023190 1194490 1021140 1194480 1021140
|
|
1194480 1015080 1194490 1015080 1194490 1013030))
|
|
(wire (path BOTTOM 700 1163940 1040000 1169300 1040000 1169300 1045210
|
|
1190950 1045210 1197940 1038220 1197940 1017920 1195940 1015920
|
|
1195940 1014480 1194490 1013030))
|
|
(wire (path BOTTOM 700 1165000 1022490 1172100 1022490 1174150 1024540
|
|
1175850 1024540 1177200 1023190 1194490 1023190))
|
|
(via VIA 1165000 1022490
|
|
(attr fanout))
|
|
(via VIA 1195000 1002780)
|
|
(via VIA 1194490 1023190)
|
|
(via VIA 1194490 1013030)
|
|
# Net RIB3_N
|
|
(wire (path TOP 700 1187000 1020000 1187000 1025240 1197050 1025240
|
|
1197050 964480 1194750 962180 1194750 957820 1198270 954300
|
|
1206150 954300 1206150 948400 1208400 946150 1211600 946150
|
|
1213850 948400 1213850 951600 1211400 954050 1211400 956280
|
|
1210580 957100 1210000 957100 1210000 960000))
|
|
# Net RIB3_P
|
|
(wire (path TOP 700 1180000 1027000 1180000 1026640 1198450 1026640
|
|
1198450 963900 1196150 961600 1196150 958400 1198850 955700
|
|
1210000 955700 1210000 950000))
|
|
# Net RIB4_N
|
|
(wire (path BOTTOM 700 1231550 1040000 1236060 1040000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1211230 1038270 1213280 1038270 1213280 1039300
|
|
1226250 1039300 1227600 1037950 1229300 1037950 1231350 1040000
|
|
1231550 1040000))
|
|
(wire (path TOP 700 1190000 1060000 1190000 1049420 1200120 1039300
|
|
1207300 1039300 1208330 1038270 1211230 1038270))
|
|
(wire (path BOTTOM 700 1211230 1038270 1211230 1034660 1230300 1034660
|
|
1230630 1034990 1233530 1034990))
|
|
(wire (path TOP 700 1233530 1034990 1235000 1033520 1235000 1027000))
|
|
(via VIA 1231550 1040000
|
|
(attr fanout))
|
|
(via VIA 1211230 1038270)
|
|
(via VIA 1233530 1034990)
|
|
# Net RIB4_P
|
|
(wire (path BOTTOM 700 1228450 1040000 1223940 1040000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1208800 1040700 1226250 1040700 1227000 1041450
|
|
1228450 1040000))
|
|
(wire (path TOP 700 1190000 1070000 1190000 1065450 1193850 1061600
|
|
1193850 1058400 1191400 1055950 1191400 1050010 1200710 1040700
|
|
1208800 1040700))
|
|
(wire (path BOTTOM 700 1208800 1040700 1208800 1037420 1209180 1037420
|
|
1209320 1037280 1209320 1033260 1229420 1033260 1229420 1032930
|
|
1231470 1032930))
|
|
(wire (path TOP 700 1231470 1032930 1231470 1030350 1230000 1030350
|
|
1230000 1027000))
|
|
(via VIA 1228450 1040000
|
|
(attr fanout))
|
|
(via VIA 1208800 1040700)
|
|
(via VIA 1231470 1032930)
|
|
# Net RIB5_N
|
|
(wire (path TOP 700 1257000 1020000 1260350 1020000 1260350 1021600
|
|
1259850 1022100 1254900 1022100 1254820 1022180 1254820 1051020
|
|
1227800 1078050 1199300 1078050 1199300 1074750 1196150 1071600
|
|
1196150 1068400 1200000 1064550 1200000 1060000))
|
|
# Net RIB5_P
|
|
(wire (path TOP 700 1250000 1027000 1250000 1023650 1251600 1023650
|
|
1252100 1024150 1252100 1029100 1253420 1030420 1253420 1050440
|
|
1227210 1076650 1200700 1076650 1200700 1070000 1200000 1070000))
|
|
# Net RIB6_N
|
|
(wire (path BOTTOM 700 1200000 960000 1200000 980000 1185000 995000
|
|
1185000 1000000 1180000 1005000 1167500 1005000 1166060 1006440
|
|
1166060 1009800))
|
|
(wire (path BOTTOM 700 1166060 1009800 1166060 1010000))
|
|
(wire (path BOTTOM 700 1166060 1009800 1161260 1005000 1145000 1005000))
|
|
(wire (path TOP 700 1145000 1005000 1153000 1005000))
|
|
(via VIA 1145000 1005000)
|
|
# Net RIB6_P
|
|
(wire (path BOTTOM 700 1200000 950000 1195050 954950 1195050 965060
|
|
1197500 967510 1197500 979300 1184300 992500 1170000 992500
|
|
1166060 996440 1166060 1000000))
|
|
(wire (path BOTTOM 700 1166060 1000000 1145000 1000000))
|
|
(wire (path TOP 700 1145000 1000000 1153000 1000000))
|
|
(via VIA 1145000 1000000)
|
|
# Net RIB7_N
|
|
(wire (path TOP 700 1160000 1027000 1160000 1023650 1157900 1023650
|
|
1157900 971690 1173890 955700 1185700 955700 1190000 960000))
|
|
# Net RIB7_P
|
|
(wire (path TOP 700 1153000 1020000 1156500 1020000 1156500 971110
|
|
1173310 954300 1185700 954300 1190000 950000))
|
|
# Net RIB8_N
|
|
(wire (path TOP 700 1210000 1060000 1210000 1055000 1207500 1052500))
|
|
(wire (path BOTTOM 700 1207500 1052500 1207500 1050440 1205000 1047940
|
|
1205000 1018200 1205700 1017500 1205700 1016800 1206440 1016060
|
|
1210000 1016060))
|
|
(wire (path BOTTOM 700 1210000 1016060 1210000 1010000))
|
|
(wire (path TOP 700 1223000 1015000 1221750 1015000 1219890 1013140
|
|
1219890 1011890 1218000 1010000 1210000 1010000))
|
|
(via VIA 1207500 1052500)
|
|
(via VIA 1210000 1010000)
|
|
# Net RIB8_P
|
|
(wire (path TOP 700 1210000 1070000 1215250 1064750 1215250 1056790
|
|
1217910 1054130 1227630 1054130 1237100 1044660 1237100 1007690
|
|
1234410 1005000 1223000 1005000))
|
|
(wire (path TOP 700 1218800 1006850 1218810 1006840 1218810 1006120
|
|
1219650 1005280 1223000 1005280 1223000 1005000))
|
|
(wire (path BOTTOM 700 1236060 1000000 1225650 1000000 1218800 1006850))
|
|
(via VIA 1218800 1006850)
|
|
# Net RIB9_N
|
|
(wire (path TOP 700 1223000 1000000 1219650 1000000 1219650 1001600
|
|
1220150 1002100 1225100 1002100 1226500 1003500 1246390 1003500
|
|
1246390 1003830 1248440 1003830))
|
|
(wire (path BOTTOM 700 1248440 1003830 1248440 1005880 1248770 1005880
|
|
1248770 1049970 1234440 1064300 1224300 1064300 1220000 1060000))
|
|
(via VIA 1248440 1003830)
|
|
# Net RIB9_P
|
|
(wire (path TOP 700 1230000 993000 1230000 1002100 1247270 1002100
|
|
1247600 1001770 1250500 1001770))
|
|
(wire (path BOTTOM 700 1250500 1001770 1250500 1004670 1250170 1005000
|
|
1250170 1050550 1235020 1065700 1224300 1065700 1220000 1070000))
|
|
(via VIA 1250500 1001770)
|
|
# Net RIB10_N
|
|
(wire (path TOP 700 1168450 980000 1168450 988300 1165000 991750
|
|
1165000 993000)
|
|
(net RIB10_N )
|
|
(type route)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1168450 980000 1163940 980000)
|
|
(net RIB10_N )
|
|
(type route)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1180000 960000 1180000 965010 1168450 976560
|
|
1168450 980000)
|
|
(net RIB10_N )
|
|
(type route))
|
|
(via VIA 1168450 980000 (net RIB10_N )
|
|
(type route)
|
|
(attr fanout))
|
|
# Net RIB10_P
|
|
(wire (path TOP 700 1171790 980000 1171790 988540 1175000 991750
|
|
1175000 993000)
|
|
(net RIB10_P )
|
|
(type route)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1180000 950000 1180000 954550 1184950 959500
|
|
1184950 962560 1171790 975720 1171790 980000)
|
|
(net RIB10_P )
|
|
(type route))
|
|
(wire (path BOTTOM 700 1176060 980000 1171790 980000)
|
|
(net RIB10_P )
|
|
(type route)
|
|
(attr fanout))
|
|
(via VIA 1171790 980000 (net RIB10_P )
|
|
(type route)
|
|
(attr fanout))
|
|
# Net SET_RETRIG1
|
|
(wire (path TOP 700 1142800 470000 1147000 470000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1142800 470000 1140000 467200 1140000 463000))
|
|
(wire (path TOP 700 1017200 475000 1013000 475000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1081840 472100 1054980 472100 1050350 467470
|
|
1050350 462850 1033800 446300 1019280 446300 1017200 448380
|
|
1017200 475000))
|
|
(wire (path TOP 700 1089610 455440 1089170 455000 1083940 455000))
|
|
(wire (path TOP 700 1164910 470000 1164910 457260 1163090 455440
|
|
1089610 455440))
|
|
(wire (path BOTTOM 700 1089610 455440 1089610 464330 1081840 472100))
|
|
(wire (path BOTTOM 700 1164910 470000 1142800 470000))
|
|
(via VIA 1017200 475000
|
|
(attr fanout))
|
|
(via VIA 1142800 470000
|
|
(attr fanout))
|
|
(via VIA 1081840 472100)
|
|
(via VIA 1089610 455440)
|
|
(via VIA 1164910 470000)
|
|
# Net SET_RETRIG2
|
|
(wire (path TOP 700 1113000 470000 1117200 470000 1120000 467200
|
|
1120000 463000))
|
|
(wire (path TOP 700 1113000 470000 1108800 470000))
|
|
(wire (path TOP 700 1047000 475000 1042800 475000 1042800 459430
|
|
1038370 455000 1033940 455000))
|
|
(wire (path TOP 700 1047000 475000 1050350 475000 1050350 500350
|
|
1062050 512050))
|
|
(wire (path BOTTOM 700 1062050 512050 1064400 512050 1066910 514560
|
|
1084870 514560 1095750 503680 1095750 492800 1098140 492800
|
|
1106060 484880 1106060 472740 1108800 470000))
|
|
(via VIA 1108800 470000)
|
|
(via VIA 1062050 512050)
|
|
# Net SMELLIE_DELAY_BUF_N
|
|
# Net SMELLIE_DELAY_BUF_P
|
|
# Net SPKR
|
|
# Net SR_CLK
|
|
(wire (path TOP 700 1132500 1319750 1132500 1305210 1134600 1303110
|
|
1134600 1300400 1135100 1299900 1135100 1263600 1132500 1261000
|
|
1132500 1259750))
|
|
(wire (path TOP 700 1132500 1319750 1132500 1327500 1120000 1340000)
|
|
(net SR_CLK ))
|
|
(wire (path TOP 700 1130000 840250 1130000 845000 1127500 847500
|
|
1105000 847500)
|
|
(net SR_CLK )
|
|
(attr fanout))
|
|
(wire (path TOP 700 1130000 840250 1130000 827500 1135000 822500
|
|
1135000 807250))
|
|
(wire (path TOP 700 266200 1336400 262100 1336400 262100 1345000
|
|
327750 1345000))
|
|
# Net SR_DATA
|
|
(wire (path TOP 700 1117500 1337500 1127500 1327500 1127500 1319750)
|
|
(net SR_DATA )
|
|
(attr fanout))
|
|
(wire (path TOP 700 1105000 850000 1134300 850000 1135000 849300
|
|
1135000 840250)
|
|
(net SR_DATA )
|
|
(attr fanout))
|
|
# Net SYNC24_2_N
|
|
(wire (path TOP 700 615000 813000 615000 803760 621060 797700
|
|
621060 797500))
|
|
(wire (path BOTTOM 700 557500 815000 617500 815000 620000 812500))
|
|
(wire (path TOP 700 615000 813000 617110 813000 617610 812500
|
|
620000 812500))
|
|
(wire (path TOP 700 552000 815000 557500 815000))
|
|
(via VIA 620000 812500)
|
|
(via VIA 557500 815000)
|
|
# Net SYNC24_2_P
|
|
(wire (path TOP 700 622000 820000 640000 820000 641440 821440
|
|
645000 821440))
|
|
(wire (path TOP 700 545000 808000 558000 808000 562500 812500
|
|
562500 817500))
|
|
(wire (path TOP 700 617500 817500 619500 817500 622000 820000))
|
|
(wire (path BOTTOM 700 562500 817500 617500 817500))
|
|
(via VIA 617500 817500)
|
|
(via VIA 562500 817500)
|
|
# Net SYNC_2_N
|
|
(wire (path TOP 700 535000 808000 535000 800700 535700 800000
|
|
580000 800000 588000 808000 588000 820000))
|
|
(wire (path TOP 700 588000 820000 578760 820000 572700 826060
|
|
572500 826060))
|
|
# Net SYNC_2_P
|
|
(wire (path TOP 700 595000 811750 595000 793760 591440 790200
|
|
591440 790000))
|
|
(wire (path TOP 700 530000 808000 530000 802500 535000 797500
|
|
580750 797500 595000 811750))
|
|
(wire (path TOP 700 595000 813000 595000 811750))
|
|
# Net TC
|
|
# Net TELLIE_DELAY_BUF_N
|
|
# Net TELLIE_DELAY_BUF_P
|
|
# Net TRIG_GATE1_N
|
|
(wire (path TOP 700 1103260 468070 1103260 468060 1100350 468060
|
|
1100040 467750 1064660 467750 1059050 462140 1059050 446560
|
|
1058440 445950 1058440 437290 1051940 437290 1051450 436800
|
|
1051450 432060 1049380 430000 1033940 430000))
|
|
(wire (path BOTTOM 700 1070000 512510 1070000 508740 1082890 508740
|
|
1091940 499680 1091940 492460 1092350 492050 1092490 492050
|
|
1092490 490000))
|
|
(wire (path TOP 700 1070000 508000 1070000 512510)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1092490 490000 1094540 490000 1094540 488440
|
|
1102930 480060 1102930 468070 1103260 468070))
|
|
(wire (path TOP 700 1092490 490000 1097000 490000)
|
|
(attr fanout))
|
|
(via VIA 1103260 468070)
|
|
(via VIA 1070000 512510
|
|
(attr fanout))
|
|
(via VIA 1092490 490000
|
|
(attr fanout))
|
|
# Net TRIG_GATE1_P
|
|
(wire (path TOP 700 1175410 472950 1176320 472040 1205000 472040
|
|
1205000 476060))
|
|
(wire (path BOTTOM 700 1142800 472950 1175410 472950))
|
|
(wire (path TOP 700 1065000 508000 1065000 504760 1066200 503560
|
|
1066510 503560)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1090000 491500 1090000 489450 1090140 489450
|
|
1091640 487950 1093050 487950 1101530 479470 1101530 469240
|
|
1101210 468920 1101210 466010 1101200 466010))
|
|
(wire (path TOP 700 1101200 466010 1101200 466350 1065240 466350
|
|
1060450 461560 1060450 442100 1065860 442100 1067960 440000
|
|
1097000 440000))
|
|
(wire (path BOTTOM 700 1066510 503560 1070280 507340 1082310 507340
|
|
1090540 499100 1090540 493550 1090000 493550 1090000 491500))
|
|
(wire (path TOP 700 1090000 491500 1090000 497000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1090000 491500 1090000 487290 1120650 487290
|
|
1120650 472950 1142800 472950))
|
|
(via VIA 1175410 472950)
|
|
(via VIA 1142800 472950)
|
|
(via VIA 1066510 503560
|
|
(attr fanout))
|
|
(via VIA 1101200 466010)
|
|
(via VIA 1090000 491500
|
|
(attr fanout))
|
|
# Net TRIG_GATE2_N
|
|
(wire (path TOP 700 1159400 459550 1155000 459550 1155000 476060))
|
|
(wire (path BOTTOM 700 1080000 503490 1081450 502040 1080850 501440
|
|
1080850 481360 1102870 459340 1157350 459340 1157350 459550
|
|
1159400 459550))
|
|
(wire (path TOP 700 1080000 508000 1080000 503490)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 500 1070000 501510 1072050 499460 1072480 499460
|
|
1072950 499930 1072950 504340 1074150 505540 1075850 505540
|
|
1077900 503490 1080000 503490))
|
|
(wire (path TOP 700 1070000 497000 1070000 501510)
|
|
(attr fanout))
|
|
(via VIA 1159400 459550)
|
|
(via VIA 1080000 503490
|
|
(attr fanout))
|
|
(via VIA 1070000 501510
|
|
(attr fanout))
|
|
# Net TRIG_GATE2_P
|
|
(wire (path TOP 700 1180000 451060 1180000 444480 1173420 437900
|
|
1127960 437900))
|
|
(wire (path TOP 700 1063000 490000 1063000 501510)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1075000 503490 1076450 502040 1078550 502040
|
|
1079450 501140 1079450 480780 1102290 457940 1158110 457940
|
|
1158560 457490 1161460 457490))
|
|
(wire (path BOTTOM 700 1066450 498060 1063000 501510))
|
|
(wire (path BOTTOM 700 1066450 498060 1070650 493860 1070650 451890
|
|
1084640 437900 1127960 437900))
|
|
(wire (path TOP 700 1161460 457490 1087860 457490 1086800 458550
|
|
1081760 458550 1081500 458810 1078440 458810 1078180 458550
|
|
1073200 458550 1072140 457490 1063000 457490 1063000 440000))
|
|
(wire (path BOTTOM 500 1075000 503490 1076740 501740 1073060 498060
|
|
1066450 498060))
|
|
(wire (path TOP 700 1075000 508000 1075000 503490)
|
|
(attr fanout))
|
|
(via VIA 1127960 437900)
|
|
(via VIA 1161460 457490)
|
|
(via VIA 1063000 501510
|
|
(attr fanout))
|
|
(via VIA 1075000 503490
|
|
(attr fanout))
|
|
# Net TRIG_PULS1_N
|
|
(wire (path TOP 700 1091500 420000 1097000 420000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1091500 420000 1088600 422900 1060140 422900
|
|
1059650 423390 1059650 426060 1055000 426060))
|
|
(wire (path TOP 700 1103490 408000 1115000 408000)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1091500 420000 1089450 420000 1089450 419860
|
|
1087950 418360 1087950 416660 1090050 414560 1090050 410800
|
|
1103490 410800 1103490 408000))
|
|
(via VIA 1091500 420000
|
|
(attr fanout))
|
|
(via VIA 1103490 408000
|
|
(attr fanout))
|
|
# Net TRIG_PULS1_P
|
|
(wire (path TOP 700 1090000 417510 1090000 413000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1090000 417510 1087950 417510 1087950 415910
|
|
1087900 415860 1087900 410140 1090000 408040 1090000 405000
|
|
1083940 405000))
|
|
(wire (path TOP 700 1108000 415000 1118860 415000 1118860 420780
|
|
1120790 422710 1180000 422710 1180000 426060))
|
|
(wire (path TOP 700 1103490 415000 1108000 415000)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1090000 417510 1091450 416060 1091450 412200
|
|
1103490 412200 1103490 415000))
|
|
(via VIA 1090000 417510
|
|
(attr fanout))
|
|
(via VIA 1103490 415000
|
|
(attr fanout))
|
|
# Net TRIG_PULS2_N
|
|
(wire (path TOP 700 1063000 420000 1053210 420000 1050960 417750
|
|
1050960 411030 1047970 408040 1037290 408040 1037290 405000
|
|
1033940 405000))
|
|
(wire (path TOP 700 1068510 420000 1063000 420000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1103490 420000 1108000 420000)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1068510 420000 1070560 420000 1070560 419850
|
|
1072050 418360 1072050 416660 1069960 414560 1069960 410900
|
|
1076370 404480 1105630 404480 1105630 418550 1104940 418550
|
|
1103490 420000))
|
|
(via VIA 1068510 420000
|
|
(attr fanout))
|
|
(via VIA 1103490 420000
|
|
(attr fanout))
|
|
# Net TRIG_PULS2_P
|
|
(wire (path TOP 700 1070000 417510 1070000 413000)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1070000 417510 1068550 416060 1068560 416060
|
|
1068560 410320 1075790 403080 1107030 403080 1107030 419950
|
|
1104030 422950 1103490 422950 1103490 425000))
|
|
(wire (path BOTTOM 700 1103490 425000 1122850 425000 1129900 417950
|
|
1202800 417950 1210910 426060))
|
|
(wire (path BOTTOM 700 1099190 414250 1100740 415800 1100740 422250
|
|
1103490 425000))
|
|
(wire (path TOP 700 1103490 425000 1108000 425000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1210910 426060 1205000 426060))
|
|
(wire (path TOP 700 1099190 414250 1099190 407050 1101590 404650
|
|
1122100 404650 1122100 414250 1147100 414250 1147100 407660
|
|
1153700 401060 1180000 401060))
|
|
(via VIA 1210910 426060)
|
|
(via VIA 1070000 417510
|
|
(attr fanout))
|
|
(via VIA 1103490 425000
|
|
(attr fanout))
|
|
(via VIA 1099190 414250)
|
|
# Net UNNAMED_1_74F06_I2_D1
|
|
# Net UNNAMED_1_74F06_I2_Q1
|
|
# Net UNNAMED_1_74F06_I3_Q1
|
|
# Net UNNAMED_1_74F07_I41_A0
|
|
# Net UNNAMED_1_74F07_I41_A1
|
|
# Net UNNAMED_1_74F07_I41_A2
|
|
# Net UNNAMED_1_74F07_I41_A3
|
|
# Net UNNAMED_1_74F07_I41_Y0
|
|
# Net UNNAMED_1_74F07_I41_Y1
|
|
# Net UNNAMED_1_74F07_I41_Y2
|
|
# Net UNNAMED_1_74F07_I41_Y3
|
|
# Net UNNAMED_1_74F164_I1_GND
|
|
(wire (path TOP 700 347250 1345000 338100 1345000 338100 1342100
|
|
312400 1342100 312400 1327900 315000 1327900 315000 1330000))
|
|
# Net UNNAMED_1_74F164_I1_VCC
|
|
(wire (path TOP 700 315000 1335200 315000 1332100 331100 1332100
|
|
331100 1327100 323000 1327100 323000 1315000 327750 1315000))
|
|
# Net UNNAMED_1_74F164_I4_Q0
|
|
# Net UNNAMED_1_74F164_I4_Q1
|
|
# Net UNNAMED_1_74F164_I4_Q2
|
|
# Net UNNAMED_1_74F164_I4_Q3
|
|
# Net UNNAMED_1_74F164_I4_Q4
|
|
# Net UNNAMED_1_74F164_I4_Q5
|
|
# Net UNNAMED_1_74F164_I4_Q6
|
|
# Net UNNAMED_1_74F164_I4_Q7
|
|
# Net UNNAMED_1_74F164_I47_Q0
|
|
# Net UNNAMED_1_74F164_I47_Q1
|
|
# Net UNNAMED_1_74F164_I47_Q2
|
|
# Net UNNAMED_1_74F164_I47_Q3
|
|
# Net UNNAMED_1_74F164_I47_Q7
|
|
# Net UNNAMED_1_74F164_I49_Q0
|
|
# Net UNNAMED_1_74F164_I49_Q1
|
|
# Net UNNAMED_1_74F164_I49_Q2
|
|
# Net UNNAMED_1_74F164_I49_Q3
|
|
# Net UNNAMED_1_74F164_I49_Q4
|
|
# Net UNNAMED_1_74F164_I49_Q5
|
|
# Net UNNAMED_1_74F164_I49_Q6
|
|
# Net UNNAMED_1_74F164_I49_Q7
|
|
# Net UNNAMED_1_7815SL_I15_INPUT
|
|
(wire (path TOP 700 205000 121310 215000 121310 215000 130000))
|
|
(wire (path TOP 700 205000 121310 205000 105000))
|
|
(wire (path TOP 700 205000 121310 205000 126060))
|
|
# Net UNNAMED_1_7915L_I16_INPUT
|
|
# Net UNNAMED_1_AD7243_I2_REFIN
|
|
# Net UNNAMED_1_AD7243_I2_VDD
|
|
# Net UNNAMED_1_AD7243_I2_VSS
|
|
# Net UNNAMED_1_AD8009_I1_IN
|
|
(wire (path TOP 700 846500 790000 848610 790000 851060 792450
|
|
851060 812500))
|
|
(wire (path TOP 700 846500 790000 851060 785440 851060 765000))
|
|
(wire (path TOP 700 846500 790000 845250 790000))
|
|
# Net UNNAMED_1_AD8009_I1_V
|
|
(wire (path TOP 700 880000 790000 864750 790000))
|
|
# Net UNNAMED_1_AD8009_I1_V_1
|
|
(wire (path TOP 700 845250 780000 827700 780000))
|
|
# Net UNNAMED_1_AD96687_I1_Q1
|
|
(wire (path TOP 700 1133940 505000 1138210 505000))
|
|
(wire (path BOTTOM 700 1138210 505000 1131260 505000 1125000 511260
|
|
1125000 517510))
|
|
(wire (path TOP 700 1125000 517510 1125000 513000)
|
|
(attr fanout))
|
|
(via VIA 1138210 505000)
|
|
(via VIA 1125000 517510
|
|
(attr fanout))
|
|
# Net UNNAMED_1_AD96687_I1_Q1_1
|
|
(wire (path TOP 700 1155000 526060 1155000 521630 1150570 517200
|
|
1140000 517200))
|
|
(wire (path TOP 700 1140000 517200 1140000 513000)
|
|
(attr fanout))
|
|
(via VIA 1140000 517200
|
|
(attr fanout))
|
|
# Net UNNAMED_1_AD96687_I1_Q2
|
|
(wire (path TOP 700 1158940 555000 1158940 558550 1156760 558550
|
|
1156500 558810 1153440 558810 1153180 558550 1148200 558550
|
|
1147710 558060 1147710 551940 1148200 551450 1152940 551450
|
|
1153440 550950 1156770 550950 1156770 543450 1156450 543130
|
|
1156450 540220 1156440 540220))
|
|
(wire (path BOTTOM 700 1142800 540000 1144850 540000 1144850 540540
|
|
1156440 540540 1156440 540220))
|
|
(wire (path TOP 700 1142800 540000 1147000 540000)
|
|
(attr fanout))
|
|
(via VIA 1156440 540220)
|
|
(via VIA 1142800 540000
|
|
(attr fanout))
|
|
# Net UNNAMED_1_AD96687_I1_Q2_1
|
|
(wire (path TOP 700 1033940 555000 1037400 555000 1037400 553390
|
|
1037890 552900 1042110 552900 1044210 555000 1063040 555000
|
|
1063390 555350 1096610 555350 1096960 555000 1110790 555000
|
|
1112890 552900 1117110 552900 1119210 555000 1122710 555000
|
|
1122710 558060 1123200 558550 1128180 558550 1128440 558810
|
|
1146480 558810 1147620 559950 1152600 559950 1152860 560210
|
|
1157080 560210 1157340 559950 1159520 559950 1160920 558550
|
|
1161800 558550 1162290 558060 1162290 551940 1161800 551450
|
|
1158500 551450 1158500 542280))
|
|
(wire (path BOTTOM 700 1135000 542490 1136450 541040 1137360 541940
|
|
1141840 541940 1141950 542050 1143650 542050 1143760 541940
|
|
1155260 541940 1155590 542270 1158500 542270 1158500 542280))
|
|
(wire (path TOP 700 1135000 542490 1135000 547000)
|
|
(attr fanout))
|
|
(via VIA 1158500 542280)
|
|
(via VIA 1135000 542490
|
|
(attr fanout))
|
|
# Net UNNAMED_1_CAENBUFFER_I5_INANAL
|
|
# Net UNNAMED_1_CAENBUFFER_I18_INANAL
|
|
# Net UNNAMED_1_CAENBUFFER_I19_INANAL
|
|
# Net UNNAMED_1_CAENBUFFER_I20_INANAL
|
|
# Net UNNAMED_1_CAENCOMS_I8_DATARDY
|
|
# Net UNNAMED_1_CAENCOMS_I8_GT2P
|
|
(wire (path TOP 700 1047000 485000 1042490 485000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 415000 995000 407000 995000)
|
|
(net UNNAMED_1_CAENCOMS_I8_GT2P )
|
|
(attr fanout))
|
|
(wire (path TOP 700 1035000 517510 1035000 513000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1017510 485000 1013000 485000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 540000 852000 540000 856200)
|
|
(net UNNAMED_1_CAENCOMS_I8_GT2P )
|
|
(attr fanout))
|
|
(wire (path TOP 700 1035000 542490 1035000 547000)
|
|
(attr fanout))
|
|
(via VIA 1042490 485000
|
|
(attr fanout))
|
|
(via VIA 1035000 517510
|
|
(attr fanout))
|
|
(via VIA 1017510 485000
|
|
(attr fanout))
|
|
(via VIA 1035000 542490
|
|
(attr fanout))
|
|
# Net UNNAMED_1_CAENCOMS_I8_GTTTL
|
|
(wire (path BOTTOM 700 610000 855000 610000 860000)
|
|
(net UNNAMED_1_CAENCOMS_I8_GTTTL )
|
|
(attr fanout))
|
|
(wire (path TOP 700 610000 855000 610000 847000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1147500 1259750 1147500 1261000 1145000 1263500
|
|
1145000 1310000 1147500 1312500 1147500 1319750))
|
|
(via VIA 610000 855000)
|
|
# Net UNNAMED_1_CAENCOMS_I8_SYNC24TTL
|
|
(wire (path TOP 700 602500 757500 607500 762500 607500 800000
|
|
610000 802500 610000 813000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 602500 757500 615000 745000)
|
|
(net UNNAMED_1_CAENCOMS_I8_SYNC24TTL )
|
|
(attr fanout))
|
|
(wire (path TOP 700 602500 757500 595250 757500)
|
|
(attr fanout))
|
|
# Net UNNAMED_1_CAENCOMS_I8_SYNCTTL
|
|
(wire (path TOP 700 598610 762500 600000 763890 600000 813000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 602500 762500 598610 762500)
|
|
(attr fanout))
|
|
(wire (path TOP 700 598610 762500 595250 762500)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 602500 762500 602500 750000 610000 742500)
|
|
(net UNNAMED_1_CAENCOMS_I8_SYNCTTL )
|
|
(attr fanout))
|
|
(via VIA 602500 762500)
|
|
# Net UNNAMED_1_CHANGECLKS_I3_BCKPC_1
|
|
# Net UNNAMED_1_CHANGECLKS_I3_BCKPC_2
|
|
# Net UNNAMED_1_CHANGECLKS_I3_BCKPC_3
|
|
# Net UNNAMED_1_CHANGECLKS_I3_BCKPCLK
|
|
# Net UNNAMED_1_CHANGECLKS_I3_CHANG_1
|
|
# Net UNNAMED_1_CHANGECLKS_I3_CHANGEC
|
|
# Net UNNAMED_1_CHANGECLKS_I3_DEFAU_1
|
|
# Net UNNAMED_1_CHANGECLKS_I3_DEFAULT
|
|
# Net UNNAMED_1_CLOCKS_I2_BCKPUSED
|
|
# Net UNNAMED_1_CLOCKS_I2_CLK100TTL
|
|
# Net UNNAMED_1_CLOCKS_I2_CLKSEL
|
|
(wire (path TOP 700 765000 442800 765000 447000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 300000 1241200 300000 1245400)
|
|
(attr fanout))
|
|
(via VIA 765000 442800
|
|
(attr fanout))
|
|
(via VIA 300000 1241200
|
|
(attr fanout))
|
|
# Net UNNAMED_1_CLOCKS_I2_DATARDY
|
|
# Net UNNAMED_1_CLOCKS_I2_RESET
|
|
(wire (path TOP 700 753000 440000 760000 440000 760000 413000))
|
|
# Net UNNAMED_1_CNTRLREGISTER_I10_DAT
|
|
(wire (path TOP 700 260000 1241200 260000 1245400)
|
|
(attr fanout))
|
|
(via VIA 260000 1241200
|
|
(attr fanout))
|
|
# Net UNNAMED_1_CNTRLREGISTER_I10_ECA
|
|
(wire (path TOP 700 407000 1065000 427500 1065000)
|
|
(net UNNAMED_1_CNTRLREGISTER_I10_ECA )
|
|
(attr fanout))
|
|
(wire (path TOP 700 427500 1065000 427500 1103700)
|
|
(net UNNAMED_1_CNTRLREGISTER_I10_ECA ))
|
|
(wire (path TOP 700 290000 1241200 290000 1245400)
|
|
(net UNNAMED_1_CNTRLREGISTER_I10_ECA ))
|
|
# Net UNNAMED_1_CNTRLREGISTER_I10_LOS
|
|
(wire (path TOP 700 295000 1241200 295000 1245400)
|
|
(attr fanout))
|
|
(via VIA 295000 1241200
|
|
(attr fanout))
|
|
# Net UNNAMED_1_CNTRLREGISTER_I10_REA
|
|
(wire (path TOP 700 266200 1338960 284360 1338960 284360 1336400
|
|
293800 1336400))
|
|
# Net UNNAMED_1_CNTRLREGISTER_I10_REG
|
|
(wire (path TOP 700 293800 1321040 299300 1321040 299300 1323600
|
|
293800 1323600))
|
|
# Net UNNAMED_1_CONN34_I1_1
|
|
# Net UNNAMED_1_COTO2342_I1_CTRLIN
|
|
# Net UNNAMED_1_COTO2342_I1_CTRLIN_1
|
|
# Net UNNAMED_1_COTO2342_I1_CTRLIN_2
|
|
# Net UNNAMED_1_COTO2342_I1_CTRLIN_3
|
|
# Net UNNAMED_1_COTO2342_I1_CTRLIN_4
|
|
# Net UNNAMED_1_COTO2342_I1_CTRLIN_5
|
|
# Net UNNAMED_1_COTO2342_I1_CTRLIN_6
|
|
# Net UNNAMED_1_COTO2342_I1_CTRLIN_7
|
|
# Net UNNAMED_1_COTO2342_I1_IN1
|
|
# Net UNNAMED_1_COTO2342_I1_IN1_1
|
|
# Net UNNAMED_1_COTO2342_I1_IN1_2
|
|
# Net UNNAMED_1_COTO2342_I1_IN1_3
|
|
# Net UNNAMED_1_COTO2342_I1_IN1_4
|
|
# Net UNNAMED_1_COTO2342_I1_IN1_5
|
|
# Net UNNAMED_1_COTO2342_I1_IN1_6
|
|
# Net UNNAMED_1_COTO2342_I1_IN1_7
|
|
# Net UNNAMED_1_COTO2342_I1_IN2
|
|
# Net UNNAMED_1_COTO2342_I1_IN2_1
|
|
# Net UNNAMED_1_COTO2342_I1_IN2_2
|
|
# Net UNNAMED_1_COTO2342_I1_IN2_3
|
|
# Net UNNAMED_1_COTO2342_I1_IN2_4
|
|
# Net UNNAMED_1_COTO2342_I1_IN2_5
|
|
# Net UNNAMED_1_COTO2342_I1_IN2_6
|
|
# Net UNNAMED_1_COTO2342_I1_IN2_7
|
|
# Net UNNAMED_1_COTO2342_I1_NC1
|
|
# Net UNNAMED_1_COTO2342_I1_NC1_1
|
|
# Net UNNAMED_1_COTO2342_I1_NC1_2
|
|
# Net UNNAMED_1_COTO2342_I1_NC1_3
|
|
# Net UNNAMED_1_COTO2342_I1_NC1_4
|
|
# Net UNNAMED_1_COTO2342_I1_NC1_5
|
|
# Net UNNAMED_1_COTO2342_I1_NC1_6
|
|
# Net UNNAMED_1_COTO2342_I1_NC1_7
|
|
# Net UNNAMED_1_COTO2342_I1_NC2
|
|
# Net UNNAMED_1_COTO2342_I1_NC2_1
|
|
# Net UNNAMED_1_COTO2342_I1_NC2_2
|
|
# Net UNNAMED_1_COTO2342_I1_NC2_3
|
|
# Net UNNAMED_1_COTO2342_I1_NC2_4
|
|
# Net UNNAMED_1_COTO2342_I1_NC2_5
|
|
# Net UNNAMED_1_COTO2342_I1_NC2_6
|
|
# Net UNNAMED_1_COTO2342_I1_NC2_7
|
|
# Net UNNAMED_1_COTO2342_I1_NO1
|
|
# Net UNNAMED_1_COTO2342_I1_NO1_1
|
|
# Net UNNAMED_1_COTO2342_I1_NO1_2
|
|
# Net UNNAMED_1_COTO2342_I1_NO1_3
|
|
# Net UNNAMED_1_COTO2342_I1_NO1_4
|
|
# Net UNNAMED_1_COTO2342_I1_NO1_5
|
|
# Net UNNAMED_1_COTO2342_I1_NO1_6
|
|
# Net UNNAMED_1_COTO2342_I1_NO1_7
|
|
# Net UNNAMED_1_COTO2342_I1_NO2
|
|
# Net UNNAMED_1_COTO2342_I1_NO2_1
|
|
# Net UNNAMED_1_COTO2342_I1_NO2_2
|
|
# Net UNNAMED_1_COTO2342_I1_NO2_3
|
|
# Net UNNAMED_1_COTO2342_I1_NO2_4
|
|
# Net UNNAMED_1_COTO2342_I1_NO2_5
|
|
# Net UNNAMED_1_COTO2342_I1_NO2_6
|
|
# Net UNNAMED_1_COTO2342_I1_NO2_7
|
|
# Net UNNAMED_1_CSMD0603_I6_A
|
|
(wire (path TOP 700 315000 1255000 305000 1255000 305000 1245400))
|
|
# Net UNNAMED_1_CSMD0603_I6_B
|
|
(wire (path TOP 700 315000 1260200 260000 1260200 260000 1280000))
|
|
# Net UNNAMED_1_CSMD0603_I10_A
|
|
# Net UNNAMED_1_CSMD0603_I10_B
|
|
# Net UNNAMED_1_CSMD0603_I10_B_1
|
|
# Net UNNAMED_1_CSMD0603_I44_A
|
|
# Net UNNAMED_1_CSMD0603_I44_B
|
|
# Net UNNAMED_1_CSMD0603_I45_A
|
|
# Net UNNAMED_1_CSMD0603_I45_B
|
|
# Net UNNAMED_1_CSMD0603_I54_B
|
|
# Net UNNAMED_1_CSMD0603_I55_A
|
|
# Net UNNAMED_1_CSMD0805_I6_A
|
|
(wire (path TOP 700 830250 1240000 824460 1245790 824460 1264500
|
|
829960 1270000 836060 1270000))
|
|
# Net UNNAMED_1_CSMD0805_I7_A_1
|
|
(wire (path TOP 700 849750 1240000 853500 1240000 854500 1239000
|
|
854500 1217000 847500 1210000 843940 1210000))
|
|
# Net UNNAMED_1_CSMD0805_I8_A_1
|
|
(wire (path TOP 700 780250 1240000 775000 1240000 770000 1245000
|
|
770000 1257950 782050 1270000 786060 1270000))
|
|
# Net UNNAMED_1_CSMD0805_I8_B
|
|
# Net UNNAMED_1_CSMD0805_I9_B
|
|
# Net UNNAMED_1_CSMD0805_I9_B_1
|
|
(wire (path TOP 700 799750 1240000 803710 1240000 808710 1235000
|
|
808710 1221000 797710 1210000 793940 1210000))
|
|
# Net UNNAMED_1_CSMD0805_I10_A
|
|
(wire (path TOP 700 899750 1247500 899750 1260630 893940 1266440
|
|
893940 1270000))
|
|
# Net UNNAMED_1_CSMD0805_I11_A
|
|
(wire (path TOP 700 880250 1232500 876500 1232500 875500 1231500
|
|
875500 1217000 882500 1210000 886060 1210000))
|
|
# Net UNNAMED_1_CSMD0805_I13_B
|
|
(wire (path TOP 700 1210000 786060 1217590 786060 1218290 786760
|
|
1218290 798600 1210000 806890 1210000 810250))
|
|
(wire (path TOP 700 1210000 786060 1195000 786060))
|
|
# Net UNNAMED_1_CSMD0805_I14_B
|
|
(wire (path TOP 700 1190000 1353940 1186440 1353940 1185000 1352500
|
|
1185000 1330000 1190000 1325000 1190000 1319750))
|
|
(wire (path TOP 700 1190000 1353940 1210000 1353940))
|
|
# Net UNNAMED_1_CSMD0805_I14_B_1
|
|
(wire (path TOP 700 1183560 863940 1195000 863940))
|
|
(wire (path TOP 700 1183560 863940 1185000 862500 1185000 829750))
|
|
(wire (path TOP 700 1183560 863940 1180000 863940))
|
|
# Net UNNAMED_1_CSMD0805_I15_B
|
|
(wire (path TOP 700 1216440 1266060 1215000 1267500 1215000 1300250))
|
|
(wire (path TOP 700 1216440 1266060 1200000 1266060))
|
|
(wire (path TOP 700 1216440 1266060 1220000 1266060))
|
|
# Net UNNAMED_1_CSMD0805_I20_B
|
|
# Net UNNAMED_1_CSMD0805_I20_B_1
|
|
# Net UNNAMED_1_CSMD0805_I20_B_2
|
|
# Net UNNAMED_1_CSMD0805_I20_B_3
|
|
# Net UNNAMED_1_CSMD0805_I20_B_4
|
|
# Net UNNAMED_1_CSMD0805_I20_B_5
|
|
# Net UNNAMED_1_CSMD0805_I20_B_6
|
|
# Net UNNAMED_1_CSMD0805_I20_B_7
|
|
# Net UNNAMED_1_CSMD0805_I21_B
|
|
# Net UNNAMED_1_CSMD0805_I21_B_1
|
|
# Net UNNAMED_1_CSMD0805_I21_B_2
|
|
# Net UNNAMED_1_CSMD0805_I21_B_3
|
|
# Net UNNAMED_1_CSMD0805_I21_B_4
|
|
# Net UNNAMED_1_CSMD0805_I21_B_5
|
|
# Net UNNAMED_1_CSMD0805_I21_B_6
|
|
# Net UNNAMED_1_CSMD0805_I21_B_7
|
|
# Net UNNAMED_1_CSMD0805_I21_B_8
|
|
# Net UNNAMED_1_CSMD0805_I22_A
|
|
# Net UNNAMED_1_CSMD0805_I22_A_1
|
|
# Net UNNAMED_1_CSMD0805_I22_A_2
|
|
# Net UNNAMED_1_CSMD0805_I22_A_3
|
|
# Net UNNAMED_1_CSMD0805_I22_A_4
|
|
# Net UNNAMED_1_CSMD0805_I22_A_5
|
|
# Net UNNAMED_1_CSMD0805_I22_A_6
|
|
# Net UNNAMED_1_CSMD0805_I22_A_7
|
|
# Net UNNAMED_1_CSMD0805_I22_B
|
|
# Net UNNAMED_1_CSMD0805_I23_A
|
|
# Net UNNAMED_1_CSMD0805_I23_A_1
|
|
# Net UNNAMED_1_CSMD0805_I23_A_2
|
|
# Net UNNAMED_1_CSMD0805_I23_A_3
|
|
# Net UNNAMED_1_CSMD0805_I23_A_4
|
|
# Net UNNAMED_1_CSMD0805_I23_A_5
|
|
# Net UNNAMED_1_CSMD0805_I23_A_6
|
|
# Net UNNAMED_1_CSMD0805_I23_A_7
|
|
# Net UNNAMED_1_CSMD0805_I23_A_8
|
|
# Net UNNAMED_1_CSMD0805_I23_B
|
|
# Net UNNAMED_1_CSMD0805_I24_B
|
|
# Net UNNAMED_1_CSMD0805_I24_B_1
|
|
# Net UNNAMED_1_CSMD0805_I24_B_2
|
|
# Net UNNAMED_1_CSMD0805_I24_B_3
|
|
# Net UNNAMED_1_CSMD0805_I24_B_4
|
|
# Net UNNAMED_1_CSMD0805_I24_B_5
|
|
# Net UNNAMED_1_CSMD0805_I24_B_6
|
|
# Net UNNAMED_1_CSMD0805_I24_B_7
|
|
# Net UNNAMED_1_CSMD0805_I46_A
|
|
(wire (path TOP 700 1172500 510550 1172500 514750)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1159550 512600 1170450 512600 1172500 510550))
|
|
(wire (path TOP 700 1159550 512600 1158550 512600 1157350 511400
|
|
1157350 508940 1155000 508940))
|
|
(via VIA 1172500 510550
|
|
(attr fanout))
|
|
(via VIA 1159550 512600)
|
|
# Net UNNAMED_1_CSMD0805_I46_B
|
|
(wire (path TOP 700 1167500 514750 1167500 512190 1163810 508500
|
|
1162090 508500 1160360 506770 1160360 503210 1158070 503210
|
|
1158070 503190 1155000 503190 1155000 501060))
|
|
(wire (path TOP 700 1167500 514750 1172490 519740 1253420 519740
|
|
1255000 521320 1255000 526060))
|
|
# Net UNNAMED_1_CSMD0805_I57_A
|
|
(wire (path TOP 700 1187500 499450 1187500 495250)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1203500 513140 1187500 513140 1187500 499450))
|
|
(wire (path TOP 700 1203500 513140 1203800 513140 1205000 511940
|
|
1205000 508940))
|
|
(via VIA 1187500 499450
|
|
(attr fanout))
|
|
(via VIA 1203500 513140)
|
|
# Net UNNAMED_1_CSMD0805_I57_B
|
|
(wire (path TOP 700 1192500 499450 1192500 495250)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1192500 468050 1200440 468050 1205000 463490
|
|
1205000 458940))
|
|
(wire (path BOTTOM 700 1192500 468050 1192500 499450))
|
|
(via VIA 1192500 499450
|
|
(attr fanout))
|
|
(via VIA 1192500 468050)
|
|
# Net UNNAMED_1_CSMD0805_I64_B
|
|
(wire (path TOP 700 1135000 408000 1135000 412200 1145000 412200))
|
|
(wire (path TOP 700 1145000 412200 1145000 408000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1184470 420000 1184470 412500 1191970 405000
|
|
1201060 405000))
|
|
(wire (path BOTTOM 700 1156510 420000 1184470 420000))
|
|
(wire (path TOP 700 1156510 420000 1152000 420000)
|
|
(attr fanout))
|
|
(via VIA 1145000 412200
|
|
(attr fanout))
|
|
(via VIA 1184470 420000)
|
|
(via VIA 1156510 420000
|
|
(attr fanout))
|
|
# Net UNNAMED_1_CSMD0805_I70_B
|
|
(wire (path TOP 700 1177650 415000 1180000 415000 1180000 408940))
|
|
(wire (path BOTTOM 700 1177650 415000 1156510 415000))
|
|
(wire (path TOP 700 1156510 415000 1152000 415000)
|
|
(attr fanout))
|
|
(via VIA 1177650 415000)
|
|
(via VIA 1156510 415000
|
|
(attr fanout))
|
|
# Net UNNAMED_1_CSMD0805_I71_A
|
|
(wire (path TOP 700 1142850 400950 1076060 400950 1076060 405000))
|
|
(wire (path TOP 700 1142850 400950 1140000 403800 1140000 408000))
|
|
(wire (path TOP 700 1142850 400950 1147490 396310 1236200 396310
|
|
1244890 405000 1251060 405000))
|
|
# Net UNNAMED_1_DEFAULTCLKSEL_I1_BCKP
|
|
# Net UNNAMED_1_DEFAULTCLKSEL_I1_DEFA
|
|
(wire (path TOP 700 867000 420000 860000 420000 860000 413000))
|
|
# Net UNNAMED_1_DEFAULTCLKSEL_I1_RESE
|
|
# Net UNNAMED_1_DS90LV019_I14_DIN
|
|
(wire (path BOTTOM 700 397500 445000 397500 450000 425000 477500
|
|
425000 525000))
|
|
(wire (path TOP 700 425000 525000 417000 525000))
|
|
(wire (path TOP 700 397500 445000 390250 445000))
|
|
(via VIA 425000 525000)
|
|
(via VIA 397500 445000)
|
|
# Net UNNAMED_1_DS90LV019_I14_ROUT
|
|
(wire (path TOP 700 390250 435000 389000 435000 376500 422500
|
|
354500 422500))
|
|
# Net UNNAMED_1_DS102350_I1_Q
|
|
(wire (path TOP 700 1130000 807250 1130000 820000 1125000 825000
|
|
1125000 840250))
|
|
# Net UNNAMED_1_ELLIECOMS_I9_SMELLI_1
|
|
# Net UNNAMED_1_ELLIECOMS_I9_SMELLIED
|
|
# Net UNNAMED_1_ELLIECOMS_I9_SMELLIEP
|
|
# Net UNNAMED_1_ELLIECOMS_I9_TELLIEDE
|
|
# Net UNNAMED_1_ELLIECOMS_I9_TELLIEPR
|
|
# Net UNNAMED_1_ELLIECOMS_I9_TELLIEPU
|
|
# Net UNNAMED_1_EXTTRIGS_I70_EXTT<10>
|
|
# Net UNNAMED_1_EXTTRIGS_I70_EXTT<11>
|
|
# Net UNNAMED_1_EXTTRIGS_I70_EXTT<12>
|
|
# Net UNNAMED_1_EXTTRIGS_I70_EXTT<13>
|
|
# Net UNNAMED_1_EXTTRIGS_I70_EXTT<14>
|
|
# Net UNNAMED_1_EXTTRIGS_I70_EXTT<15>
|
|
# Net UNNAMED_1_EXTTRIGS_I70_EXTTR<0>
|
|
# Net UNNAMED_1_EXTTRIGS_I70_EXTTR<1>
|
|
# Net UNNAMED_1_EXTTRIGS_I70_EXTTR<2>
|
|
# Net UNNAMED_1_EXTTRIGS_I70_EXTTR<3>
|
|
# Net UNNAMED_1_EXTTRIGS_I70_EXTTR<4>
|
|
# Net UNNAMED_1_EXTTRIGS_I70_EXTTR<5>
|
|
# Net UNNAMED_1_EXTTRIGS_I70_EXTTR<6>
|
|
# Net UNNAMED_1_EXTTRIGS_I70_EXTTR<7>
|
|
# Net UNNAMED_1_EXTTRIGS_I70_EXTTR<8>
|
|
# Net UNNAMED_1_EXTTRIGS_I70_EXTTR<9>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_CAEN<0>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_CAEN<1>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_CAEN<2>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_CAEN<3>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_CAEN<4>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_CAEN<5>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_CAEN<6>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_CAEN<7>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_CLK100N
|
|
# Net UNNAMED_1_FRONTPORTS_I2_CLK100P
|
|
# Net UNNAMED_1_FRONTPORTS_I2_DGTN
|
|
# Net UNNAMED_1_FRONTPORTS_I2_DGTP
|
|
# Net UNNAMED_1_FRONTPORTS_I2_ECLTO_1
|
|
(wire (path TOP 700 432500 437500 417500 437500 415000 435000
|
|
409750 435000)
|
|
(net UNNAMED_1_FRONTPORTS_I2_ECLTO_1 )
|
|
(attr fanout))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_ECLTO_2
|
|
(wire (path TOP 700 432500 440000 409750 440000)
|
|
(net UNNAMED_1_FRONTPORTS_I2_ECLTO_2 )
|
|
(attr fanout))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_ECLTO_3
|
|
(wire (path TOP 700 345000 470000 470000 470000 472500 467500
|
|
472500 465000 475000 462500)
|
|
(net UNNAMED_1_FRONTPORTS_I2_ECLTO_3 ))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_ECLTO_4
|
|
(wire (path TOP 700 430000 560000 449510 540490 449510 539510
|
|
425000 515000 417000 515000)
|
|
(net UNNAMED_1_FRONTPORTS_I2_ECLTO_4 ))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_ECLTOLV
|
|
(wire (path BOTTOM 700 440000 523940 443560 523940 445000 522500
|
|
447500 522500 460000 535000 465000 535000))
|
|
(wire (path TOP 700 465000 535000 458000 535000))
|
|
(via VIA 465000 535000)
|
|
# Net UNNAMED_1_FRONTPORTS_I2_ECLTONI
|
|
(wire (path TOP 700 457500 562500 467500 552500 480750 552500
|
|
490000 543250)
|
|
(net UNNAMED_1_FRONTPORTS_I2_ECLTONI ))
|
|
(wire (path BOTTOM 700 490000 550000 496260 550000 506060 559800
|
|
506060 560000))
|
|
(wire (path TOP 700 490000 550000 490000 543250))
|
|
(wire (path TOP 700 490000 543250 490000 542000))
|
|
(via VIA 490000 550000)
|
|
# Net UNNAMED_1_FRONTPORTS_I2_ECLTOTT
|
|
(wire (path BOTTOM 700 470000 547500 470000 553740 476060 559800
|
|
476060 560000))
|
|
(wire (path TOP 700 470000 547500 470000 543250))
|
|
(wire (path TOP 700 470000 543250 453250 560000 452500 560000)
|
|
(net UNNAMED_1_FRONTPORTS_I2_ECLTOTT ))
|
|
(wire (path TOP 700 470000 543250 470000 542000))
|
|
(via VIA 470000 547500)
|
|
# Net UNNAMED_1_FRONTPORTS_I2_EXT<10>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_EXT<11>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_EXT<12>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_EXT<13>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_EXT<14>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_EXT<15>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_EXTPEDI
|
|
(wire (path TOP 700 400000 997500 400000 1007000))
|
|
(wire (path BOTTOM 700 400000 997500 393940 997500))
|
|
(via VIA 400000 997500)
|
|
# Net UNNAMED_1_FRONTPORTS_I2_EXTPEDO
|
|
(wire (path TOP 700 407000 980000 405750 980000 403500 977750
|
|
403500 974390 402110 973000 400000 973000))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_EXTT<0>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_EXTT<1>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_EXTT<2>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_EXTT<3>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_EXTT<4>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_EXTT<5>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_EXTT<6>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_EXTT<7>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_EXTT<8>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_EXTT<9>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_GENER_1
|
|
(wire (path TOP 700 1145000 786500 1145000 775000 1150000 770000)
|
|
(net UNNAMED_1_FRONTPORTS_I2_GENER_1 )
|
|
(attr fanout))
|
|
(wire (path TOP 700 1145000 786500 1145000 787750)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1145000 786500 1149000 782500 1165000 782500
|
|
1185000 802500 1185000 810250)
|
|
(attr fanout))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_GENER_2
|
|
(wire (path TOP 700 1159300 855000 1162500 855000 1170000 847500
|
|
1170000 832500 1182500 820000 1201500 820000 1210000 828500
|
|
1210000 829750)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1159300 855000 1121390 855000 1120000 856390
|
|
1120000 859750)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1159300 855000 1159300 871800)
|
|
(net UNNAMED_1_FRONTPORTS_I2_GENER_2 )
|
|
(attr fanout))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_GENERIC
|
|
# Net UNNAMED_1_FRONTPORTS_I2_GTN
|
|
(wire (path BOTTOM 700 526060 822500 526060 828940 525000 830000))
|
|
(wire (path TOP 700 508000 845000 506750 845000 502620 840870
|
|
502620 839130 506750 835000 508000 835000))
|
|
(wire (path TOP 700 520000 852000 520000 853250 515750 857500
|
|
512500 857500 508000 853000 508000 845000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 508000 835000 512500 835000 517500 830000
|
|
525000 830000))
|
|
(via VIA 525000 830000)
|
|
# Net UNNAMED_1_FRONTPORTS_I2_GTNIM
|
|
(wire (path TOP 700 522400 782500 526250 778650 526250 778500))
|
|
(wire (path TOP 700 522400 782500 522050 782850 520890 782850
|
|
513940 789800 513940 790000))
|
|
(wire (path TOP 700 522400 782500 519900 780000 510000 780000)
|
|
(net UNNAMED_1_FRONTPORTS_I2_GTNIM ))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_GTP
|
|
(wire (path BOTTOM 700 526060 840000 525000 841060 525000 845000))
|
|
(wire (path TOP 700 525000 852000 525000 848640))
|
|
(wire (path TOP 700 525000 845000 525000 848640))
|
|
(wire (path TOP 700 525000 848640 523640 848640 520000 845000
|
|
515700 845000 515000 845700))
|
|
(wire (path TOP 700 508000 840000 511360 840000 515000 843640
|
|
515000 845700))
|
|
(wire (path TOP 700 515000 845700 515000 852000))
|
|
(via VIA 525000 845000)
|
|
# Net UNNAMED_1_FRONTPORTS_I2_LOSTA_1
|
|
# Net UNNAMED_1_FRONTPORTS_I2_LOSTARO
|
|
# Net UNNAMED_1_FRONTPORTS_I2_LVDST_1
|
|
(wire (path TOP 700 427500 382500 427500 427500 425000 430000
|
|
409750 430000)
|
|
(net UNNAMED_1_FRONTPORTS_I2_LVDST_1 )
|
|
(attr fanout))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_LVDST_2
|
|
(wire (path TOP 700 302500 427500 320500 427500)
|
|
(net UNNAMED_1_FRONTPORTS_I2_LVDST_2 ))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_LVDSTOE
|
|
(wire (path TOP 700 425000 382500 425000 424300 424300 425000
|
|
409750 425000)
|
|
(net UNNAMED_1_FRONTPORTS_I2_LVDSTOE )
|
|
(attr fanout))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_MTCAM_1
|
|
(wire (path TOP 700 1120000 447800 1120000 452000)
|
|
(attr fanout))
|
|
(via VIA 1120000 447800
|
|
(attr fanout))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_MTCAM_2
|
|
# Net UNNAMED_1_FRONTPORTS_I2_MTCAM_3
|
|
(wire (path TOP 700 1112200 435000 1108000 435000)
|
|
(attr fanout))
|
|
(via VIA 1112200 435000
|
|
(attr fanout))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_MTCAM_4
|
|
(wire (path TOP 700 1112200 440000 1108000 440000)
|
|
(attr fanout))
|
|
(via VIA 1112200 440000
|
|
(attr fanout))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_MTCAM_5
|
|
# Net UNNAMED_1_FRONTPORTS_I2_MTCAMIM
|
|
(wire (path TOP 700 1115000 447800 1115000 452000)
|
|
(attr fanout))
|
|
(via VIA 1115000 447800
|
|
(attr fanout))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_MTCDLO
|
|
(wire (path TOP 700 852500 1041060 863580 1041060 864640 1040000
|
|
868000 1040000))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_NIMTO_1
|
|
# Net UNNAMED_1_FRONTPORTS_I2_NIMTOEC
|
|
(wire (path TOP 700 462500 570000 465000 567500 527500 567500
|
|
544000 551000 544000 548750)
|
|
(net UNNAMED_1_FRONTPORTS_I2_NIMTOEC ))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_PUL<10>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_PUL<11>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_PULS<0>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_PULS<1>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_PULS<2>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_PULS<3>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_PULS<4>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_PULS<5>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_PULS<6>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_PULS<7>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_PULS<8>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_PULS<9>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_PULSE_1
|
|
(wire (path TOP 700 864750 785000 861390 785000 858940 782550
|
|
858940 765000))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_PULSEIN
|
|
# Net UNNAMED_1_FRONTPORTS_I2_RIBBO_1
|
|
# Net UNNAMED_1_FRONTPORTS_I2_RIBBO_2
|
|
# Net UNNAMED_1_FRONTPORTS_I2_RIBBO_3
|
|
# Net UNNAMED_1_FRONTPORTS_I2_RIBBONP
|
|
# Net UNNAMED_1_FRONTPORTS_I2_SCAL<1>
|
|
(wire (path TOP 700 275000 1241200 275000 1245400)
|
|
(attr fanout))
|
|
(via VIA 275000 1241200
|
|
(attr fanout))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_SCAL<2>
|
|
(wire (path TOP 700 280000 1241200 280000 1245400)
|
|
(attr fanout))
|
|
(via VIA 280000 1241200
|
|
(attr fanout))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_SCAL<3>
|
|
(wire (path TOP 700 285000 1241200 285000 1245400)
|
|
(attr fanout))
|
|
(via VIA 285000 1241200
|
|
(attr fanout))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_SCAL<4>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_SCAL<5>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_SCAL<6>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_SCOP<0>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_SCOP<1>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_SCOP<2>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_SCOP<3>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_SCOP<4>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_SCOP<5>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_SCOP<6>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_SCOP<7>
|
|
# Net UNNAMED_1_FRONTPORTS_I2_SMELL_1
|
|
# Net UNNAMED_1_FRONTPORTS_I2_SMELL_2
|
|
# Net UNNAMED_1_FRONTPORTS_I2_SMELLIE
|
|
# Net UNNAMED_1_FRONTPORTS_I2_SYNC2_1
|
|
(wire (path TOP 700 642500 757500 614750 757500)
|
|
(net UNNAMED_1_FRONTPORTS_I2_SYNC2_1 )
|
|
(attr fanout))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_SYNC24L
|
|
(wire (path TOP 700 642500 755000 640000 752500 614750 752500)
|
|
(net UNNAMED_1_FRONTPORTS_I2_SYNC24L )
|
|
(attr fanout))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_SYNC24N
|
|
(wire (path TOP 700 520000 808000 520000 800000)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 520000 800000 520000 797500 517500 795000
|
|
515000 795000 512500 797500 492500 797500 490000 795000
|
|
490000 781260 483940 775200 483940 775000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 520000 800000 517500 797500 512500 797500
|
|
510000 800000 457500 800000)
|
|
(net UNNAMED_1_FRONTPORTS_I2_SYNC24N )
|
|
(attr fanout))
|
|
(via VIA 520000 800000
|
|
(attr fanout))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_SYNC24P
|
|
(wire (path BOTTOM 700 515000 800000 491240 800000 483940 792700
|
|
483940 792500)
|
|
(attr fanout))
|
|
(wire (path TOP 700 515000 806750 515000 808000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 515000 806750 515000 800000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 515000 806750 510750 802500 457500 802500)
|
|
(net UNNAMED_1_FRONTPORTS_I2_SYNC24P )
|
|
(attr fanout))
|
|
(via VIA 515000 800000
|
|
(attr fanout))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_SYNCL_1
|
|
(wire (path TOP 700 642500 762500 614750 762500)
|
|
(net UNNAMED_1_FRONTPORTS_I2_SYNCL_1 )
|
|
(attr fanout))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_SYNCLVD
|
|
(wire (path TOP 700 645000 765000 642500 767500 614750 767500)
|
|
(net UNNAMED_1_FRONTPORTS_I2_SYNCLVD )
|
|
(attr fanout))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_SYNCN
|
|
(wire (path BOTTOM 700 480000 806060 483560 806060 484120 805500
|
|
508000 805500))
|
|
(wire (path TOP 700 508000 815000 508000 805500))
|
|
(via VIA 508000 805500)
|
|
# Net UNNAMED_1_FRONTPORTS_I2_SYNCP
|
|
(wire (path BOTTOM 700 480000 826060 511440 826060 515000 822500
|
|
515000 820000))
|
|
(wire (path TOP 700 508000 820000 515000 820000))
|
|
(via VIA 515000 820000)
|
|
# Net UNNAMED_1_FRONTPORTS_I2_TELLI_1
|
|
# Net UNNAMED_1_FRONTPORTS_I2_TELLIED
|
|
# Net UNNAMED_1_FRONTPORTS_I2_TELLIEP
|
|
# Net UNNAMED_1_FRONTPORTS_I2_TTLTO_1
|
|
(wire (path TOP 700 302500 422500 320500 422500)
|
|
(net UNNAMED_1_FRONTPORTS_I2_TTLTO_1 ))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_TTLTOEC
|
|
(wire (path TOP 700 307500 405000 341800 405000 342500 405700
|
|
342500 415500)
|
|
(net UNNAMED_1_FRONTPORTS_I2_TTLTOEC ))
|
|
# Net UNNAMED_1_FRONTPORTS_I2_TUBCLKI
|
|
(wire (path TOP 700 840010 435000 833000 435000))
|
|
(wire (path BOTTOM 700 862060 435000 840010 435000))
|
|
(wire (path TOP 700 862060 435000 862060 440000 867000 440000))
|
|
(via VIA 840010 435000)
|
|
(via VIA 862060 435000)
|
|
# Net UNNAMED_1_FRONTPORTS_I2_TUBIIRT
|
|
# Net UNNAMED_1_GENERALUTILITIES_I4_1
|
|
# Net UNNAMED_1_GENERALUTILITIES_I4_G
|
|
# Net UNNAMED_1_GTDELAYS_I1_DDGTN
|
|
(wire (path TOP 700 873000 990000 869640 990000 868580 988940
|
|
852500 988940))
|
|
# Net UNNAMED_1_GTDELAYS_I1_DDGTP
|
|
# Net UNNAMED_1_HCT123_I9_Q1
|
|
# Net UNNAMED_1_HCT123_I9_Q2
|
|
# Net UNNAMED_1_HCT123_I22_Q1
|
|
(wire (path TOP 700 1195000 822500 1195000 829750)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1195000 822500 1205000 822500 1237500 790000)
|
|
(net UNNAMED_1_HCT123_I22_Q1 )
|
|
(attr fanout))
|
|
(via VIA 1195000 822500)
|
|
# Net UNNAMED_1_HCT123_I22_Q2
|
|
(wire (path TOP 700 1200000 817500 1200000 810250)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1200000 817500 1205000 817500 1237500 785000)
|
|
(net UNNAMED_1_HCT123_I22_Q2 )
|
|
(attr fanout))
|
|
(via VIA 1200000 817500)
|
|
# Net UNNAMED_1_HCT123_I29_CEXT1
|
|
# Net UNNAMED_1_HCT123_I54_INB1
|
|
(wire (path TOP 700 1085000 492800 1085000 497000)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1197160 488240 1197160 461700 1134280 461700
|
|
1133630 461050 1103210 461050 1085000 479260 1085000 492800))
|
|
(wire (path TOP 700 1197160 488240 1180070 488240 1178460 489850
|
|
1168700 489850 1167500 491050 1167500 495250))
|
|
(via VIA 1085000 492800
|
|
(attr fanout))
|
|
(via VIA 1197160 488240)
|
|
# Net UNNAMED_1_HCT123_I54_INB2
|
|
(wire (path BOTTOM 700 1108110 463100 1195110 463100 1195110 507940
|
|
1192500 510550))
|
|
(wire (path TOP 700 1108110 463100 1108110 467040 1105020 470130
|
|
1101930 470130 1099960 472100 1085350 472100 1075000 482450
|
|
1075000 497000))
|
|
(wire (path TOP 700 1192500 510550 1192500 514750)
|
|
(attr fanout))
|
|
(via VIA 1192500 510550
|
|
(attr fanout))
|
|
(via VIA 1108110 463100)
|
|
# Net UNNAMED_1_HCT123_I54_Q1
|
|
(wire (path TOP 700 1177500 510550 1177500 514750)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1255000 515190 1182140 515190 1177500 510550))
|
|
(wire (path TOP 700 1255000 515190 1255000 508940))
|
|
(via VIA 1177500 510550
|
|
(attr fanout))
|
|
(via VIA 1255000 515190)
|
|
# Net UNNAMED_1_HCT123_I54_Q2
|
|
(wire (path TOP 700 1182500 495250 1182500 490410 1228380 490410
|
|
1230000 488790 1230000 483940))
|
|
# Net UNNAMED_1_HCT238_I53_A0
|
|
# Net UNNAMED_1_HCT238_I53_A1
|
|
# Net UNNAMED_1_HCT238_I53_A2
|
|
# Net UNNAMED_1_HCT374_I2_Q6
|
|
(wire (path TOP 700 270000 1245400 270000 1230000 280000 1230000))
|
|
# Net UNNAMED_1_HCT374_I2_Q7
|
|
(wire (path TOP 700 265000 1245400 265000 1230000 255000 1230000))
|
|
# Net UNNAMED_1_INDUCTORL_I3_A
|
|
(wire (path TOP 700 255000 155000 256740 156740 275500 156740))
|
|
# Net UNNAMED_1_INDUCTORL_I4_A
|
|
(wire (path BOTTOM 700 355000 205000 334500 184500 334500 156740))
|
|
# Net UNNAMED_1_INDUCTORL_I5_A
|
|
# Net UNNAMED_1_INDUCTORL_I6_A
|
|
# Net UNNAMED_1_LEDL_I3_A
|
|
# Net UNNAMED_1_LEDL_I11_A
|
|
# Net UNNAMED_1_LEDL_I12_A
|
|
# Net UNNAMED_1_LEDL_I13_A
|
|
# Net UNNAMED_1_LEDL_I14_A
|
|
# Net UNNAMED_1_LEDL_I17_A
|
|
# Net UNNAMED_1_LEDL_I18_A
|
|
# Net UNNAMED_1_LEDL_I18_A_1
|
|
# Net UNNAMED_1_LEDL_I19_A
|
|
# Net UNNAMED_1_LEDL_I19_B
|
|
# Net UNNAMED_1_LEDL_I25_A
|
|
# Net UNNAMED_1_LEDL_I32_A
|
|
# Net UNNAMED_1_LEDL_I33_A
|
|
# Net UNNAMED_1_LEDL_I42_B
|
|
# Net UNNAMED_1_LEDL_I44_A
|
|
# Net UNNAMED_1_LEDL_I46_B
|
|
# Net UNNAMED_1_LEDL_I49_A
|
|
# Net UNNAMED_1_LEDL_I50_A
|
|
# Net UNNAMED_1_LM337TL_I14_REF
|
|
(wire (path TOP 700 230000 225150 196310 225150 196310 255000
|
|
201060 255000))
|
|
(wire (path TOP 700 230000 225150 230000 205000 251060 205000))
|
|
(wire (path TOP 700 230000 225150 230000 230000))
|
|
# Net UNNAMED_1_LOGEN_I13_DGT2
|
|
# Net UNNAMED_1_LOGEN_I13_LOSTAR2
|
|
# Net UNNAMED_1_MC10E116_I1_D0
|
|
# Net UNNAMED_1_MC10E116_I1_Q0
|
|
# Net UNNAMED_1_MC10E116_I1_Q0_1
|
|
# Net UNNAMED_1_MC10E116_I1_Q3
|
|
(wire (path TOP 700 622000 840000 641240 840000 644800 843560
|
|
645000 843560))
|
|
(wire (path TOP 700 552000 845000 582500 845000 585000 842500
|
|
592510 842500 595010 840000 622000 840000))
|
|
# Net UNNAMED_1_MC10E116_I1_Q3_1
|
|
(wire (path TOP 700 615000 847000 615000 860380 616060 861440
|
|
616060 865000))
|
|
(wire (path TOP 700 552000 840000 547500 840000 546800 840700
|
|
546800 846800 547500 847500 582500 847500 585000 845000
|
|
592040 845000 594540 842500 613860 842500 615000 843640
|
|
615000 847000))
|
|
# Net UNNAMED_1_MC10E116_I2_D0
|
|
(wire (path TOP 700 868000 1045000 869250 1045000 874510 1039740))
|
|
(wire (path TOP 700 868000 1035000 869250 1035000 871110 1036860
|
|
871630 1036860 874510 1039740))
|
|
(wire (path TOP 700 880000 1028000 880000 1034250 874510 1039740))
|
|
# Net UNNAMED_1_MC10E116_I2_Q0
|
|
(wire (path TOP 700 885000 1005000 885000 997000))
|
|
(wire (path BOTTOM 700 887500 1007500 921060 1007500))
|
|
(wire (path BOTTOM 700 885000 1005000 887500 1007500))
|
|
(wire (path BOTTOM 700 890000 1022500 890000 1010000 887500 1007500))
|
|
(wire (path TOP 700 890000 1022500 890000 1028000))
|
|
(via VIA 885000 1005000)
|
|
(via VIA 890000 1022500)
|
|
# Net UNNAMED_1_MC10E116_I3_Q0
|
|
# Net UNNAMED_1_MC10E116_I3_Q0_1
|
|
# Net UNNAMED_1_MC10E116_I3_Q1
|
|
# Net UNNAMED_1_MC10E116_I3_Q1_1
|
|
# Net UNNAMED_1_MC10E116_I3_Q2
|
|
# Net UNNAMED_1_MC10E116_I3_Q2_1
|
|
# Net UNNAMED_1_MC10E116_I3_Q3
|
|
# Net UNNAMED_1_MC10E116_I3_Q3_1
|
|
# Net UNNAMED_1_MC10E116_I4_Q0
|
|
# Net UNNAMED_1_MC10E116_I4_Q0_1
|
|
# Net UNNAMED_1_MC10E116_I4_Q1
|
|
# Net UNNAMED_1_MC10E116_I4_Q1_1
|
|
# Net UNNAMED_1_MC10E116_I4_Q2
|
|
# Net UNNAMED_1_MC10E116_I4_Q2_1
|
|
# Net UNNAMED_1_MC10E116_I4_Q3
|
|
# Net UNNAMED_1_MC10E116_I4_Q3_1
|
|
# Net UNNAMED_1_MC10E116_I22_D3
|
|
(wire (path TOP 700 544000 541250 544000 536380 551440 528940
|
|
555000 528940))
|
|
(wire (path TOP 700 544000 541250 536250 541250 530000 535000
|
|
502000 535000))
|
|
# Net UNNAMED_1_MC10E116_I22_Q0
|
|
(wire (path BOTTOM 700 410000 510000 408310 511690 407050 511690
|
|
403940 514800 403940 515000))
|
|
(wire (path TOP 700 458000 520000 456750 520000 454250 517500
|
|
435000 517500 427500 510000 417000 510000))
|
|
(wire (path TOP 700 417000 510000 410000 510000))
|
|
(via VIA 410000 510000)
|
|
# Net UNNAMED_1_MC10E116_I22_Q0_1
|
|
(wire (path TOP 700 410000 503000 410000 486260 403940 480200
|
|
403940 480000))
|
|
(wire (path TOP 700 458000 515000 435000 515000 423000 503000
|
|
410000 503000))
|
|
# Net UNNAMED_1_MC10E116_I22_Q1
|
|
(wire (path TOP 700 410000 537000 410000 545380 411060 546440
|
|
411060 550000))
|
|
(wire (path BOTTOM 700 442500 502500 440000 502500 430000 512500
|
|
430000 535000))
|
|
(wire (path TOP 700 458000 505000 445000 505000 442500 502500))
|
|
(wire (path TOP 700 430000 535000 428000 537000 410000 537000))
|
|
(via VIA 430000 535000)
|
|
(via VIA 442500 502500)
|
|
# Net UNNAMED_1_MC10E116_I22_Q1_1
|
|
(wire (path BOTTOM 700 410000 530000 403940 530000))
|
|
(wire (path TOP 700 427500 530000 417000 530000))
|
|
(wire (path BOTTOM 700 440500 498000 427500 511000 427500 530000))
|
|
(wire (path TOP 700 465000 498000 440500 498000))
|
|
(wire (path TOP 700 410000 530000 417000 530000))
|
|
(via VIA 410000 530000)
|
|
(via VIA 427500 530000)
|
|
(via VIA 440500 498000)
|
|
# Net UNNAMED_1_MC10E116_I22_Q2
|
|
(wire (path TOP 700 475000 482500 480000 477500 491060 477500))
|
|
(wire (path TOP 700 475000 482500 475000 475000 480000 470000
|
|
480000 462500))
|
|
(wire (path TOP 700 475000 482500 475000 498000))
|
|
# Net UNNAMED_1_MC10E116_I63_Q0
|
|
(wire (path TOP 700 1055000 446560 1055000 451060))
|
|
(wire (path TOP 700 1090340 427460 1114150 427460 1114150 430000
|
|
1152000 430000))
|
|
(wire (path TOP 700 1090340 427460 1092800 425000 1097000 425000))
|
|
(wire (path TOP 700 1067340 430170 1087630 430170 1090340 427460))
|
|
(wire (path BOTTOM 700 1067340 430170 1067340 434220 1055000 446560))
|
|
(via VIA 1055000 446560)
|
|
(via VIA 1067340 430170)
|
|
# Net UNNAMED_1_MC10E116_I63_Q1
|
|
(wire (path TOP 700 1059050 494350 1059050 476060 1055000 476060))
|
|
(wire (path BOTTOM 700 1069400 428110 1070250 428960 1080690 428960))
|
|
(wire (path BOTTOM 700 1059050 494350 1059050 450600 1080690 428960))
|
|
(wire (path BOTTOM 700 1146600 444950 1145100 443450 1144500 443450
|
|
1130010 428960 1080690 428960))
|
|
(wire (path TOP 700 1146600 444950 1148650 444950 1148650 445000
|
|
1152000 445000))
|
|
(wire (path TOP 700 1069400 428110 1069400 427100 1063000 427100
|
|
1063000 425000)
|
|
(attr fanout))
|
|
(via VIA 1059050 494350)
|
|
(via VIA 1146600 444950)
|
|
(via VIA 1069400 428110
|
|
(attr fanout))
|
|
# Net UNNAMED_1_MC10H131_I17_CE1
|
|
(wire (path TOP 700 1020000 517200 1020000 513000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1020000 542800 1020000 547000)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1020000 542800 1020000 517200))
|
|
(via VIA 1020000 517200
|
|
(attr fanout))
|
|
(via VIA 1020000 542800
|
|
(attr fanout))
|
|
# Net UNNAMED_1_MICROZEDMODULE_I1_MTC
|
|
# Net UNNAMED_1_MMBTH81_I9_C
|
|
(wire (path TOP 700 533560 752500 533560 767840 530050 771350
|
|
530050 771500))
|
|
# Net UNNAMED_1_MPSH81_I17_C
|
|
(wire (path TOP 700 448940 460000 467500 460000 470000 462500))
|
|
# Net UNNAMED_1_PRMA1C05B_I33_CTRLIN
|
|
# Net UNNAMED_1_PRMA1C05B_I34_CTRLIN
|
|
# Net UNNAMED_1_PRMA1C05B_I39_CTRLIN
|
|
# Net UNNAMED_1_PRMA1C05B_I40_CTRLIN
|
|
# Net UNNAMED_1_RESL_I7_A
|
|
# Net UNNAMED_1_RESL_I7_A_1
|
|
# Net UNNAMED_1_RESL_I7_A_2
|
|
# Net UNNAMED_1_RESL_I7_A_3
|
|
# Net UNNAMED_1_RESL_I7_A_4
|
|
# Net UNNAMED_1_RESL_I7_A_5
|
|
# Net UNNAMED_1_RESL_I7_A_6
|
|
# Net UNNAMED_1_RESL_I7_A_7
|
|
# Net UNNAMED_1_RESL_I10_B
|
|
# Net UNNAMED_1_RESL_I10_B_1
|
|
# Net UNNAMED_1_RESL_I10_B_2
|
|
# Net UNNAMED_1_RESL_I10_B_3
|
|
# Net UNNAMED_1_RESL_I10_B_4
|
|
# Net UNNAMED_1_RESL_I10_B_5
|
|
# Net UNNAMED_1_RESL_I10_B_6
|
|
# Net UNNAMED_1_RESL_I10_B_7
|
|
# Net UNNAMED_1_RESL_I11_A
|
|
# Net UNNAMED_1_RESL_I11_A_1
|
|
# Net UNNAMED_1_RESL_I11_A_2
|
|
# Net UNNAMED_1_RESL_I11_A_3
|
|
# Net UNNAMED_1_RESL_I11_A_4
|
|
# Net UNNAMED_1_RESL_I11_A_5
|
|
# Net UNNAMED_1_RESL_I11_A_6
|
|
# Net UNNAMED_1_RESL_I11_A_7
|
|
# Net UNNAMED_1_RESL_I11_B
|
|
# Net UNNAMED_1_RESL_I11_B_1
|
|
# Net UNNAMED_1_RESL_I11_B_2
|
|
# Net UNNAMED_1_RESL_I11_B_3
|
|
# Net UNNAMED_1_RESL_I11_B_4
|
|
# Net UNNAMED_1_RESL_I11_B_5
|
|
# Net UNNAMED_1_RESL_I11_B_6
|
|
# Net UNNAMED_1_RESL_I11_B_7
|
|
# Net UNNAMED_1_RESL_I16_A
|
|
# Net UNNAMED_1_RESL_I16_A_1
|
|
# Net UNNAMED_1_RESL_I16_A_2
|
|
# Net UNNAMED_1_RESL_I16_A_3
|
|
# Net UNNAMED_1_RESL_I16_A_4
|
|
# Net UNNAMED_1_RESL_I16_A_5
|
|
# Net UNNAMED_1_RESL_I16_A_6
|
|
# Net UNNAMED_1_RESL_I16_A_7
|
|
# Net UNNAMED_1_RESL_I16_B
|
|
# Net UNNAMED_1_RESL_I16_B_1
|
|
# Net UNNAMED_1_RESL_I16_B_2
|
|
# Net UNNAMED_1_RESL_I16_B_3
|
|
# Net UNNAMED_1_RESL_I16_B_4
|
|
# Net UNNAMED_1_RESL_I16_B_5
|
|
# Net UNNAMED_1_RESL_I16_B_6
|
|
# Net UNNAMED_1_RESL_I16_B_7
|
|
# Net UNNAMED_1_RSMD0805_I4_B
|
|
# Net UNNAMED_1_RSMD0805_I5_B
|
|
# Net UNNAMED_1_RSMD0805_I16_B
|
|
(wire (path TOP 700 785550 489600 783450 487500 770250 487500))
|
|
(wire (path TOP 700 785550 489600 820000 489600 820000 506060))
|
|
(wire (path BOTTOM 700 785550 557500 785550 489600))
|
|
(wire (path TOP 700 785550 557500 793500 557500))
|
|
(via VIA 785550 489600)
|
|
(via VIA 785550 557500)
|
|
# Net UNNAMED_1_RSMD0805_I17_B
|
|
(wire (path TOP 700 774450 492500 770250 492500))
|
|
(wire (path TOP 700 793500 552500 808050 552500 808050 532710
|
|
820000 532710 820000 536060))
|
|
(wire (path TOP 700 793500 552500 774450 552500))
|
|
(wire (path BOTTOM 700 774450 552500 774450 492500))
|
|
(via VIA 774450 492500)
|
|
(via VIA 774450 552500)
|
|
# Net UNNAMED_1_RSMD0805_I18_B
|
|
# Net UNNAMED_1_RSMD0805_I18_B_1
|
|
# Net UNNAMED_1_RSMD0805_I18_B_2
|
|
# Net UNNAMED_1_RSMD0805_I18_B_3
|
|
# Net UNNAMED_1_RSMD0805_I18_B_4
|
|
# Net UNNAMED_1_RSMD0805_I18_B_5
|
|
# Net UNNAMED_1_RSMD0805_I18_B_6
|
|
# Net UNNAMED_1_RSMD0805_I18_B_7
|
|
# Net UNNAMED_1_RSMD0805_I31_A
|
|
# Net UNNAMED_1_SS22SDP2_I34_P1
|
|
(wire (path TOP 700 1135000 518400 1135000 513000))
|
|
(wire (path BOTTOM 700 1122940 539950 1122940 530460 1135000 518400))
|
|
(wire (path TOP 700 1122940 539950 1137290 539950 1137290 555000
|
|
1133940 555000))
|
|
(via VIA 1135000 518400)
|
|
(via VIA 1122940 539950)
|
|
# Net UNNAMED_1_SS22SDP2_I34_P2
|
|
(wire (path TOP 700 1142800 520000 1147000 520000)
|
|
(attr fanout))
|
|
(via VIA 1142800 520000
|
|
(attr fanout))
|
|
# Net UNNAMED_1_SS22SDP2_I34_TA1
|
|
# Net UNNAMED_1_SS22SDP2_I34_TA2
|
|
# Net UNNAMED_1_SS22SDP2_I35_P1
|
|
(wire (path TOP 700 1140000 551200 1140000 547000)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1184510 551060 1140140 551060 1140000 551200))
|
|
(wire (path TOP 700 1184510 551060 1180000 551060))
|
|
(via VIA 1140000 551200
|
|
(attr fanout))
|
|
(via VIA 1184510 551060)
|
|
# Net UNNAMED_1_SS22SDP2_I35_P2
|
|
(wire (path TOP 700 1125000 542800 1125000 547000)
|
|
(attr fanout))
|
|
(wire (path BOTTOM 700 1180000 521790 1165240 536550 1140550 536550
|
|
1140550 537050 1130750 537050 1125000 542800))
|
|
(wire (path TOP 700 1180000 521790 1180000 526060))
|
|
(via VIA 1125000 542800
|
|
(attr fanout))
|
|
(via VIA 1180000 521790)
|
|
# Net USE_BCKP_N
|
|
# Net USE_BCKP_P
|
|
# Net USE_DEFAULT_N
|
|
# Net USE_DEFAULT_P
|
|
# Net V3P3
|
|
(wire (path BOTTOM 700 355000 189540 804050 189540 804050 515450
|
|
806100 517500))
|
|
(wire (path TOP 700 355000 189540 355000 183940))
|
|
(wire (path TOP 700 355000 189540 342950 201590 342950 229850
|
|
330000 229850 330000 242400))
|
|
(wire (path TOP 700 788750 562500 788750 566000 857300 566000
|
|
857300 522300 825950 522300 823550 519900 823550 517500
|
|
806100 517500))
|
|
(wire (path TOP 700 806100 517500 793500 517500))
|
|
(wire (path TOP 700 788750 562500 759850 562500))
|
|
(wire (path TOP 700 788750 562500 793500 562500))
|
|
(wire (path TOP 700 759850 562500 759850 554600 744800 554600
|
|
744800 550000))
|
|
(wire (path TOP 700 759850 562500 756500 562500))
|
|
(via VIA 806100 517500)
|
|
(via VIA 355000 189540)
|
|
# Net VBB_TRANS
|
|
(wire (path TOP 700 475000 537500 467500 530000 458000 530000))
|
|
(wire (path TOP 700 475000 542000 475000 540750))
|
|
(wire (path TOP 700 475000 540750 471790 537540 468210 537540
|
|
465000 540750 465000 542000))
|
|
(wire (path TOP 700 475000 537500 475000 540750))
|
|
(wire (path BOTTOM 700 475000 537500 485000 537500))
|
|
(wire (path TOP 700 485000 537500 485000 542000))
|
|
(wire (path TOP 700 495000 540750 495000 542000))
|
|
(wire (path TOP 700 495000 540750 495000 530000 497500 527500
|
|
507500 527500 508940 528940 530000 528940))
|
|
(wire (path TOP 700 485000 537500 491750 537500 495000 540750))
|
|
(via VIA 475000 537500)
|
|
(via VIA 485000 537500)
|
|
# Net VCC
|
|
(wire (path TOP 700 320940 242400 320940 237700))
|
|
(wire (path TOP 700 305000 1280000 305000 1275800)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1063000 475000 1067200 475000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1162500 514750 1162500 510550)
|
|
(attr fanout))
|
|
(wire (path TOP 700 407500 1075000 407000 1074500 407000 1070000))
|
|
(wire (path TOP 700 390250 450000 380000 450000))
|
|
(wire (path TOP 700 748800 425000 753000 425000))
|
|
(wire (path TOP 700 760000 451200 760000 447000))
|
|
(wire (path TOP 700 347500 419700 347500 415500))
|
|
(wire (path TOP 700 401440 407500 401440 442940 408500 450000
|
|
409750 450000))
|
|
(wire (path TOP 700 407500 407500 401440 407500))
|
|
(wire (path TOP 700 395000 537000 395000 540360 392860 542500
|
|
367500 542500 365000 540000 365000 533940))
|
|
(wire (path TOP 700 372500 537500 368940 533940 365000 533940))
|
|
(wire (path BOTTOM 700 385000 1070000 385000 1062600))
|
|
(wire (path TOP 700 385000 1077000 385000 1070000))
|
|
(wire (path TOP 700 385000 1085000 385000 1077000))
|
|
(wire (path TOP 700 355000 990100 355000 997500 360000 1002500
|
|
391750 1002500 395000 1005750 395000 1007000))
|
|
(wire (path TOP 700 359900 990100 355000 990100))
|
|
(wire (path TOP 700 615000 835000 622000 835000))
|
|
(wire (path TOP 700 632500 835000 622000 835000))
|
|
(wire (path BOTTOM 700 607600 835000 615000 835000))
|
|
(wire (path TOP 700 595250 767500 591890 767500 586990 762600
|
|
582500 762600))
|
|
(wire (path TOP 700 582500 767500 582500 762600))
|
|
(wire (path TOP 700 347500 437500 354500 437500))
|
|
(wire (path BOTTOM 700 341440 440000 345000 440000 347500 437500))
|
|
(via VIA 320940 237700 (contact VCC))
|
|
(via VIA 305000 1275800
|
|
(attr fanout) (contact VCC))
|
|
(via VIA 1067200 475000
|
|
(attr fanout) (contact VCC))
|
|
(via VIA 1162500 510550
|
|
(attr fanout) (contact VCC))
|
|
(via VIA 407500 1075000 (contact VCC))
|
|
(via VIA 380000 450000 (contact VCC))
|
|
(via VIA 748800 425000 (contact VCC))
|
|
(via VIA 760000 451200 (contact VCC))
|
|
(via VIA 347500 419700 (contact VCC))
|
|
(via VIA 407500 407500 (contact VCC))
|
|
(via VIA 372500 537500 (contact VCC))
|
|
(via VIA 385000 1070000 (contact VCC))
|
|
(via VIA 385000 1085000 (contact VCC))
|
|
(via VIA 359900 990100 (contact VCC))
|
|
(via VIA 615000 835000 (contact VCC))
|
|
(via VIA 632500 835000 (contact VCC))
|
|
(via VIA 582500 767500 (contact VCC))
|
|
(via VIA 347500 437500 (contact VCC))
|
|
# Net VCC15
|
|
(wire (path TOP 700 180000 80000 200000 80000 205000 85000))
|
|
# Net VCC15M
|
|
# Net VEE
|
|
(wire (path TOP 700 1130000 408000 1130000 403800)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1085000 447000 1085000 442800)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1063000 485000 1067200 485000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1080000 552000 1080000 547800)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1013000 535000 1017200 535000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1025000 463000 1025000 467200)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1135000 497000 1135000 492800)
|
|
(attr fanout))
|
|
(wire (path TOP 700 1147000 525000 1142800 525000)
|
|
(attr fanout))
|
|
(wire (path TOP 700 508000 830000 502500 830000 497500 835000
|
|
497500 847510 495110 849900 492500 849900))
|
|
(wire (path TOP 700 492500 849900 492500 842500))
|
|
(wire (path TOP 700 541440 752500 550000 752500))
|
|
(wire (path TOP 700 555000 521060 548560 521060 547500 520000))
|
|
(wire (path TOP 700 441060 460000 441060 453560 440000 452500))
|
|
(wire (path TOP 700 752300 517500 756500 517500))
|
|
(wire (path TOP 700 748800 435000 753000 435000))
|
|
(wire (path TOP 700 855000 452510 855000 447000))
|
|
(wire (path TOP 700 766050 507500 770250 507500))
|
|
(wire (path BOTTOM 700 615000 825000 607600 825000))
|
|
(wire (path TOP 700 622000 825000 615000 825000))
|
|
(wire (path TOP 700 622000 825000 632500 825000))
|
|
(wire (path BOTTOM 700 395000 1070000 395000 1062600))
|
|
(wire (path TOP 700 395000 1077000 395000 1070000))
|
|
(wire (path TOP 700 395000 1077000 395000 1085000))
|
|
(wire (path BOTTOM 700 480000 530000 480000 515600 477400 513000
|
|
477400 512500))
|
|
(wire (path BOTTOM 700 477400 512500 472500 512500))
|
|
(wire (path TOP 700 480000 542000 480000 530000))
|
|
(wire (path TOP 700 405000 537000 405000 538250 398250 545000
|
|
355000 545000 350000 540000 350000 533940))
|
|
(wire (path TOP 700 350000 533940 353940 533940 357500 537500))
|
|
(wire (path TOP 700 347500 427500 354500 427500))
|
|
(wire (path BOTTOM 700 341440 425000 345000 425000 347500 427500))
|
|
(via VIA 1130000 403800
|
|
(attr fanout) (contact VEE))
|
|
(via VIA 1085000 442800
|
|
(attr fanout) (contact VEE))
|
|
(via VIA 1067200 485000
|
|
(attr fanout) (contact VEE))
|
|
(via VIA 1080000 547800
|
|
(attr fanout) (contact VEE))
|
|
(via VIA 1017200 535000
|
|
(attr fanout) (contact VEE))
|
|
(via VIA 1025000 467200
|
|
(attr fanout) (contact VEE))
|
|
(via VIA 1135000 492800
|
|
(attr fanout) (contact VEE))
|
|
(via VIA 1142800 525000
|
|
(attr fanout) (contact VEE))
|
|
(via VIA 492500 842500 (contact VEE))
|
|
(via VIA 550000 752500 (contact VEE))
|
|
(via VIA 547500 520000 (contact VEE))
|
|
(via VIA 440000 452500 (contact VEE))
|
|
(via VIA 752300 517500 (contact VEE))
|
|
(via VIA 748800 435000 (contact VEE))
|
|
(via VIA 855000 452510 (contact VEE))
|
|
(via VIA 766050 507500 (contact VEE))
|
|
(via VIA 632500 825000 (contact VEE))
|
|
(via VIA 615000 825000 (contact VEE))
|
|
(via VIA 395000 1085000 (contact VEE))
|
|
(via VIA 395000 1070000 (contact VEE))
|
|
(via VIA 472500 512500 (contact VEE))
|
|
(via VIA 480000 530000 (contact VEE))
|
|
(via VIA 357500 537500 (contact VEE))
|
|
(via VIA 347500 427500 (contact VEE))
|
|
# Net VREF5M
|
|
# Net VREF5M_1
|
|
# Net VREF5M_2
|
|
# Net VREF5M_3
|
|
# Net VREF5M_4
|
|
# Net VREF5M_5
|
|
# Net VREF5M_6
|
|
# Net VREF5M_7
|
|
# Net VTT
|
|
(wire (path TOP 700 852500 1011440 852500 1017500))
|
|
(wire (path BOTTOM 700 928940 1007500 928940 1003560 930000 1002500))
|
|
(wire (path BOTTOM 700 893940 1040000 893940 1043940 895000 1045000))
|
|
(wire (path TOP 700 845000 1047500 847060 1047500 848500 1048940
|
|
852500 1048940))
|
|
(wire (path BOTTOM 700 533940 822500 533940 818560 535000 817500))
|
|
(wire (path BOTTOM 700 533940 840000 533940 833560 535000 832500))
|
|
(wire (path BOTTOM 700 476060 775000 476060 781060 477500 782500))
|
|
(wire (path BOTTOM 700 476060 792500 476060 788560 475000 787500))
|
|
(wire (path BOTTOM 700 480000 813940 473940 813940 472500 812500))
|
|
(wire (path BOTTOM 700 480000 833940 480000 842500))
|
|
(wire (path TOP 700 583560 790000 577500 790000))
|
|
(wire (path TOP 700 572500 833940 572500 840000))
|
|
(wire (path TOP 700 645000 813560 645000 807500))
|
|
(wire (path TOP 700 628940 797500 635000 797500))
|
|
(wire (path TOP 700 541440 790000 547500 790000))
|
|
(wire (path BOTTOM 700 386060 997500 386060 993120 385000 992060
|
|
385000 990000))
|
|
(wire (path BOTTOM 700 386060 982500 380000 982500))
|
|
(wire (path BOTTOM 700 483940 560000 492500 560000))
|
|
(wire (path BOTTOM 700 513940 560000 520000 560000))
|
|
(wire (path BOTTOM 700 440000 516060 440000 510000))
|
|
(wire (path TOP 700 418940 550000 425000 550000))
|
|
(wire (path BOTTOM 700 396060 515000 390000 515000))
|
|
(wire (path TOP 700 396060 480000 390000 480000))
|
|
(wire (path TOP 700 498940 477500 507500 477500))
|
|
(wire (path BOTTOM 700 927500 986060 927500 980000))
|
|
(wire (path TOP 700 623940 865000 630000 865000))
|
|
(wire (path TOP 700 645000 851440 645000 857500))
|
|
(wire (path BOTTOM 700 396060 530000 390000 530000))
|
|
(via VIA 852500 1017500 (contact VTT))
|
|
(via VIA 930000 1002500 (contact VTT))
|
|
(via VIA 895000 1045000 (contact VTT))
|
|
(via VIA 845000 1047500 (contact VTT))
|
|
(via VIA 535000 817500 (contact VTT))
|
|
(via VIA 535000 832500 (contact VTT))
|
|
(via VIA 477500 782500 (contact VTT))
|
|
(via VIA 475000 787500 (contact VTT))
|
|
(via VIA 472500 812500 (contact VTT))
|
|
(via VIA 480000 842500 (contact VTT))
|
|
(via VIA 577500 790000 (contact VTT))
|
|
(via VIA 572500 840000 (contact VTT))
|
|
(via VIA 645000 807500 (contact VTT))
|
|
(via VIA 635000 797500 (contact VTT))
|
|
(via VIA 547500 790000 (contact VTT))
|
|
(via VIA 385000 990000 (contact VTT))
|
|
(via VIA 380000 982500 (contact VTT))
|
|
(via VIA 492500 560000 (contact VTT))
|
|
(via VIA 520000 560000 (contact VTT))
|
|
(via VIA 440000 510000 (contact VTT))
|
|
(via VIA 425000 550000 (contact VTT))
|
|
(via VIA 390000 515000 (contact VTT))
|
|
(via VIA 390000 480000 (contact VTT))
|
|
(via VIA 507500 477500 (contact VTT))
|
|
(via VIA 927500 980000 (contact VTT))
|
|
(via VIA 630000 865000 (contact VTT))
|
|
(via VIA 645000 857500 (contact VTT))
|
|
(via VIA 390000 530000 (contact VTT))
|
|
)
|