| .. |
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signoise.run
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Did (most of) Gt Delays. Changed some parts
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2015-02-28 01:58:57 -05:00 |
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.rtcomp
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Did and Fixed all dangling net report
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2015-05-22 11:46:15 -04:00 |
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allegro_P00416.6_AllegroMiniDump.dmp
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Changed via-line spacing to 10 mils and fixed DRCs
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2015-05-19 19:36:46 -04:00 |
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allegro.jrl
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Bookkeeping update, no real changes
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2015-09-07 11:41:52 -04:00 |
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allegro.jrl,1
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Bookkeeping update, no real changes
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2015-09-07 11:41:52 -04:00 |
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aperture.log
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Changed LVPECL pulldwn. Made much art-ty changes
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2015-05-21 18:45:00 -04:00 |
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aperture.log,1
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Messing around with gerbers
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2015-05-20 19:27:46 -04:00 |
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aperture.log,2
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Messing around with gerbers
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2015-05-20 19:27:46 -04:00 |
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aperture.log,3
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Changed LVPECL pulldwn. Made much art-ty changes
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2015-05-21 18:45:00 -04:00 |
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art_aper.txt
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Messing around with gerbers
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2015-05-20 19:27:46 -04:00 |
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art_aper.txt,1
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Changed LVPECL pulldwn. Made much art-ty changes
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2015-05-21 18:45:00 -04:00 |
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art_param.txt
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Expanded board by 0.2 inches vertically. Doing manufacture prep
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2015-05-20 13:59:39 -04:00 |
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art_param.txt,1
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Fixed reed relay pins. Created Gerbers
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2015-05-20 17:49:41 -04:00 |
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AUTOSAVE.brd
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Many changes. Added 74lv07a to caen anal stuff
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2015-05-26 17:34:42 -04:00 |
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autosilk.log
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Fixed DS1023 package.
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2015-06-02 11:32:17 -04:00 |
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autosilk.log,1
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Fixed DS1023 package.
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2015-06-02 11:32:17 -04:00 |
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autosilk.log,2
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Fixed DS1023 package.
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2015-06-02 11:32:17 -04:00 |
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autosilk.log,3
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Changed DS1023 from soic to soicw
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2015-06-01 13:43:47 -04:00 |
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batch_drc.log
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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batch_drc.log,1
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Changed DS1023 from soic to soicw
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2015-06-01 13:43:47 -04:00 |
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batch_drc.log,2
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Changed DS1023 from soic to soicw
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2015-06-01 13:43:47 -04:00 |
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batch_drc.log,3
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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bestsave.w
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Placed all the rooms
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2015-03-09 14:40:42 -04:00 |
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BSTPLC.brd
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Began arranging fault_detection parts
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2015-04-16 20:12:10 -04:00 |
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BSTPLC.brd,1
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Began arranging fault_detection parts
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2015-04-16 20:12:10 -04:00 |
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caen_buf_mod_v1.mdd
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Replicated CAEN_BUF
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2015-03-25 16:56:09 -04:00 |
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caen_buf_mod_v2.mdd
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Arranged digital parts of CAEN_ANALOG block
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2015-03-27 11:59:56 -04:00 |
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dangling_lines.rpt,1
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Made VREFM into a plane. Fixed DRCs and Danglers
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2015-05-27 16:00:46 -04:00 |
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dbdoctor.log
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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dbdoctor.log,1
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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dbdoctor.log,2
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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dbdoctor.log,3
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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delete_layer_objects.rpt
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Fixed problem with GND_Bot not connecting to GNDs
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2015-05-27 16:33:36 -04:00 |
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delete_layer_objects.rpt,1
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Fixed problem with GND_Bot not connecting to GNDs
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2015-05-27 16:33:36 -04:00 |
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devices.dml
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Did (most of) Gt Delays. Changed some parts
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2015-02-28 01:58:57 -05:00 |
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dfa_constraints.par
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Finished all layout crap. Added Neutrino Atlas
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2015-05-31 17:16:36 -04:00 |
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dxf2a.log
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Finished all layout crap. Added Neutrino Atlas
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2015-05-31 17:16:36 -04:00 |
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dxf2a.log,1
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Finished all layout crap. Added Neutrino Atlas
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2015-05-31 17:16:36 -04:00 |
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dxf2a.log,2
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Finished all layout crap. Added Neutrino Atlas
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2015-05-31 17:16:36 -04:00 |
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dxf2a.log,3
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Finished all layout crap. Added Neutrino Atlas
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2015-05-31 17:16:36 -04:00 |
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eco.txt
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Changed 1n5822 package to do201AD
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2015-06-04 15:18:08 -04:00 |
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eco.txt,1
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Changed 1n5822 package to do201AD
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2015-06-04 15:18:08 -04:00 |
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extract.log
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Changed DS1023 from soic to soicw
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2015-06-01 13:43:47 -04:00 |
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extract.log,1
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Changed 1n5822 package to do201AD
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2015-06-04 15:18:08 -04:00 |
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extract.log,2
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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extract.log,3
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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extract.txt
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Commiting here b/c synching isn't changing layout...needs to be fixed
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2015-05-12 19:56:40 -04:00 |
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genfeed.log
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Commiting here b/c synching isn't changing layout...needs to be fixed
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2015-05-12 19:56:40 -04:00 |
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genfeed.log,1
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Commiting here b/c synching isn't changing layout...needs to be fixed
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2015-05-12 19:56:40 -04:00 |
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gloss.log
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Did and Fixed all dangling net report
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2015-05-22 11:46:15 -04:00 |
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interconn.iml
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Changed LVPECL pulldwn. Made much art-ty changes
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2015-05-21 18:45:00 -04:00 |
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interconn.iml,1
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Changed LVPECL pulldwn. Made much art-ty changes
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2015-05-21 18:45:00 -04:00 |
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load_photoplot.log
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Added a note for d6r10 push button
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2015-06-08 16:53:59 -04:00 |
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load_photoplot.log,1
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Added a note for d6r10 push button
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2015-06-08 16:53:59 -04:00 |
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load_photoplot.log,2
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Added a note for d6r10 push button
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2015-06-08 16:53:59 -04:00 |
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load_photoplot.log,3
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Added a note for d6r10 push button
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2015-06-08 16:53:59 -04:00 |
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marzece_TUBII_6_5_BOTTOM_Production.art
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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marzece_TUBII_6_5_Drill_Production.art
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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marzece_TUBII_6_5_GND_BOT_Production.art
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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marzece_TUBII_6_5_GND_TOP_Production.art
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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marzece_TUBII_6_5_SilkScreen_Bottom_Production.art
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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marzece_TUBII_6_5_SilkScreen_Top_Production.art
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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marzece_TUBII_6_5_SolderMask_Bottom_Production.art
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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marzece_TUBII_6_5_SolderMask_Top_Production.art
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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marzece_TUBII_6_5_TOP_Production.art
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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marzece_TUBII_6_5_VCC_Production.art
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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marzece_TUBII_6_5_VEE_Production.art
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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marzece_TUBII_6_5_VPM15_Production.art
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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marzece_TUBII_6_5_VTT_Production.art
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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marzece_TubiiPCB_prod-1-8.drl
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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marzece_TubiiPCB_prod-1-8.drl,1
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Fixed DS1023 package.
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2015-06-02 11:32:17 -04:00 |
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master.tag
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Commiting here b/c synching isn't changing layout...needs to be fixed
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2015-05-12 19:56:40 -04:00 |
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monitor.sts
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Routed the last route
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2015-04-23 11:29:06 -04:00 |
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myfavorites.txt
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Improved readability and added mounting holes
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2015-05-03 19:09:48 -04:00 |
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myfavorites.txt,1
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Improved readability and added mounting holes
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2015-05-03 19:09:48 -04:00 |
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nc_param.txt
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Changed DS1023 from soic to soicw
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2015-06-01 13:43:47 -04:00 |
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nc_param.txt,1
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Changed DS1023 from soic to soicw
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2015-06-01 13:43:47 -04:00 |
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ncdrill.log
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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ncdrill.log,1
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Changed 1n5822 package to do201AD
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2015-06-04 15:18:08 -04:00 |
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ncdrill.log,2
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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ncdrill.log,3
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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nclegend.log
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Added a note for d6r10 push button
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2015-06-08 16:53:59 -04:00 |
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nclegend.log,1
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Remade artwork (which I sent to the PCB company)
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2015-06-05 11:17:39 -04:00 |
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nclegend.log,2
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Added a note for d6r10 push button
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2015-06-08 16:53:59 -04:00 |
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nclegend.log,3
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Added a note for d6r10 push button
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2015-06-08 16:53:59 -04:00 |
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netlist.txt
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Used josh's script to look for missing Rs. None found
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2015-05-22 19:18:43 -04:00 |
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netrev.lst
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Changed 1n5822 package to do201AD
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2015-06-04 15:18:08 -04:00 |
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OpenGLInfo.log
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Added voids on all planes for THS3062
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2015-05-11 17:10:37 -04:00 |
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perf_advisor.log
|
Changed via-line spacing to 10 mils and fixed DRCs
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2015-05-19 19:36:46 -04:00 |
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perf_advisor.log,1
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Changed line spacing DRCs...started fixing
|
2015-05-19 20:05:36 -04:00 |
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perf_advisor.log,2
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Changed via-line spacing to 10 mils and fixed DRCs
|
2015-05-19 19:36:46 -04:00 |
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perf_advisor.log,3
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Changed via-line spacing to 10 mils and fixed DRCs
|
2015-05-19 19:36:46 -04:00 |
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photoplot.log
|
Remade artwork (which I sent to the PCB company)
|
2015-06-05 11:17:39 -04:00 |
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photoplot.log,1
|
Remade artwork (which I sent to the PCB company)
|
2015-06-05 11:17:39 -04:00 |
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photoplot.log,2
|
Remade artwork (which I sent to the PCB company)
|
2015-06-05 11:17:39 -04:00 |
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photoplot.log,3
|
Remade artwork (which I sent to the PCB company)
|
2015-06-05 11:17:39 -04:00 |
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place_txt.txt
|
Expanded board by 0.2 inches vertically. Doing manufacture prep
|
2015-05-20 13:59:39 -04:00 |
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place.log
|
Began arranging fault_detection parts
|
2015-04-16 20:12:10 -04:00 |
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place.log,1
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Began arranging fault_detection parts
|
2015-04-16 20:12:10 -04:00 |
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place.log,2
|
Began arranging fault_detection parts
|
2015-04-16 20:12:10 -04:00 |
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place.log,3
|
Began arranging fault_detection parts
|
2015-04-16 20:12:10 -04:00 |
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plctxt.log
|
Expanded board by 0.2 inches vertically. Doing manufacture prep
|
2015-05-20 13:59:39 -04:00 |
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pstcmdb2.dat
|
Changed 1n5822 package to do201AD
|
2015-06-04 15:18:08 -04:00 |
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quickplace.log
|
Routing loose ends...nearly done
|
2015-04-23 04:41:37 -04:00 |
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quickplace.log,1
|
Routing loose ends...nearly done
|
2015-04-23 04:41:37 -04:00 |
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quickplace.log,2
|
Routing loose ends...nearly done
|
2015-04-23 04:41:37 -04:00 |
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quickplace.log,3
|
Routing loose ends...nearly done
|
2015-04-23 04:41:37 -04:00 |
|
rename.log
|
Changed DS1023 from soic to soicw
|
2015-06-01 13:43:47 -04:00 |
|
router.log
|
Did and Fixed all dangling net report
|
2015-05-22 11:46:15 -04:00 |
|
signoise.log
|
Remade artwork (which I sent to the PCB company)
|
2015-06-05 11:17:39 -04:00 |
|
signoise.log,1
|
Remade artwork (which I sent to the PCB company)
|
2015-06-05 11:17:39 -04:00 |
|
signoise.log,2
|
Remade artwork (which I sent to the PCB company)
|
2015-06-05 11:17:39 -04:00 |
|
signoise.log,3
|
Remade artwork (which I sent to the PCB company)
|
2015-06-05 11:17:39 -04:00 |
|
specctra.did
|
Routed the last route
|
2015-04-23 11:29:06 -04:00 |
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specctra.did,1
|
Routed the last route
|
2015-04-23 11:29:06 -04:00 |
|
specctra.log
|
Routed the last route
|
2015-04-23 11:29:06 -04:00 |
|
specctra.log,1
|
Routed the last route
|
2015-04-23 11:29:06 -04:00 |
|
specctra.log,2
|
Routed the last route
|
2015-04-23 11:29:06 -04:00 |
|
specctra.log,3
|
Routed the last route
|
2015-04-23 11:29:06 -04:00 |
|
Tubii_DFA.dfa
|
Many changes. Added 74lv07a to caen anal stuff
|
2015-05-26 17:34:42 -04:00 |
|
TubiiPCB_prod-1-7-1-7.drl
|
Added connects to unconnected GNDs & PWRs
|
2015-05-22 14:42:27 -04:00 |
|
TubiiPCB_prod-1-8.drl
|
Changed DS1023 from soic to soicw
|
2015-06-01 13:43:47 -04:00 |
|
TubiiPCB_test-1-7-1-8.drl
|
Changed DS1023 from soic to soicw
|
2015-06-01 13:43:47 -04:00 |
|
TubiiPCB_test-1-7.drl
|
Changed LVPECL pulldwn. Made much art-ty changes
|
2015-05-21 18:45:00 -04:00 |
|
TubiiPCB_V1.brd
|
Finshed off LO_Gen and did minor routing
|
2015-02-28 18:43:30 -05:00 |
|
TubiiPCB_V2_forget.do
|
Did layout for gen_delays and pulse_inv
|
2015-03-08 17:59:06 -04:00 |
|
TubiiPCB_V2_rules.do
|
Did layout for gen_delays and pulse_inv
|
2015-03-08 17:59:06 -04:00 |
|
TubiiPCB_V2.brd
|
Did layout for gen_delays and pulse_inv
|
2015-03-08 17:59:06 -04:00 |
|
TubiiPCB_V2.dsn
|
Did layout for gen_delays and pulse_inv
|
2015-03-08 17:59:06 -04:00 |
|
TubiiPCB_V3.brd
|
Added voids on all planes for THS3062
|
2015-05-11 17:10:37 -04:00 |
|
TubiiPCB_V3.SAV
|
Added voids on all planes for THS3062
|
2015-05-11 17:10:37 -04:00 |
|
TubiiPCB_V4.brd
|
Did routing for vcc15/vcc15m
|
2015-05-11 19:51:47 -04:00 |
|
TubiiPCB_V4.SAV
|
Finshed 15v planes and 3.3v one.
|
2015-05-12 16:16:08 -04:00 |
|
TubiiPCB_V5.brd
|
Commiting here b/c synching isn't changing layout...needs to be fixed
|
2015-05-12 19:56:40 -04:00 |
|
TubiiPCB_V6.brd
|
Bookkeeping update, no real changes
|
2015-09-07 11:41:52 -04:00 |
|
TubiiPCB_V6.brd.lck
|
Bookkeeping update, no real changes
|
2015-09-07 11:41:52 -04:00 |
|
TubiiPCB_V6.SAV
|
Changed via-line spacing to 10 mils and fixed DRCs
|
2015-05-19 19:36:46 -04:00 |
|
window_drc.log
|
Changed via-line spacing to 10 mils and fixed DRCs
|
2015-05-19 19:36:46 -04:00 |
|
window_drc.log,1
|
Changed via-line spacing to 10 mils and fixed DRCs
|
2015-05-19 19:36:46 -04:00 |
|
window_drc.log,2
|
Changed via-line spacing to 10 mils and fixed DRCs
|
2015-05-19 19:36:46 -04:00 |
|
window_drc.log,3
|
Changed via-line spacing to 10 mils and fixed DRCs
|
2015-05-19 19:36:46 -04:00 |
|
xsectionChart.log
|
Expanded board by 0.2 inches vertically. Doing manufacture prep
|
2015-05-20 13:59:39 -04:00 |
|
xsectionChart.log,1
|
Expanded board by 0.2 inches vertically. Doing manufacture prep
|
2015-05-20 13:59:39 -04:00 |
|
xsectionChart.log,2
|
Fixed reed relay pins. Created Gerbers
|
2015-05-20 17:49:41 -04:00 |
|
xsectionChart.log,3
|
Fixed reed relay pins. Created Gerbers
|
2015-05-20 17:49:41 -04:00 |
|
xsectionChartParams.txt
|
Fixed reed relay pins. Created Gerbers
|
2015-05-20 17:49:41 -04:00 |
