Eric Marzec bd255ca0a8 Bookkeeping update, no real changes

2015-09-07 11:41:52 -04:00

..

signoise.run

Did (most of) Gt Delays. Changed some parts

2015-02-28 01:58:57 -05:00

.rtcomp

Did and Fixed all dangling net report

2015-05-22 11:46:15 -04:00

allegro_P00416.6_AllegroMiniDump.dmp

Changed via-line spacing to 10 mils and fixed DRCs

2015-05-19 19:36:46 -04:00

allegro.jrl

Bookkeeping update, no real changes

2015-09-07 11:41:52 -04:00

allegro.jrl,1

Bookkeeping update, no real changes

2015-09-07 11:41:52 -04:00

aperture.log

Changed LVPECL pulldwn. Made much art-ty changes

2015-05-21 18:45:00 -04:00

aperture.log,1

Messing around with gerbers

2015-05-20 19:27:46 -04:00

aperture.log,2

Messing around with gerbers

2015-05-20 19:27:46 -04:00

aperture.log,3

Changed LVPECL pulldwn. Made much art-ty changes

2015-05-21 18:45:00 -04:00

art_aper.txt

Messing around with gerbers

2015-05-20 19:27:46 -04:00

art_aper.txt,1

Changed LVPECL pulldwn. Made much art-ty changes

2015-05-21 18:45:00 -04:00

art_param.txt

Expanded board by 0.2 inches vertically. Doing manufacture prep

2015-05-20 13:59:39 -04:00

art_param.txt,1

Fixed reed relay pins. Created Gerbers

2015-05-20 17:49:41 -04:00

AUTOSAVE.brd

Many changes. Added 74lv07a to caen anal stuff

2015-05-26 17:34:42 -04:00

autosilk.log

Fixed DS1023 package.

2015-06-02 11:32:17 -04:00

autosilk.log,1

Fixed DS1023 package.

2015-06-02 11:32:17 -04:00

autosilk.log,2

Fixed DS1023 package.

2015-06-02 11:32:17 -04:00

autosilk.log,3

Changed DS1023 from soic to soicw

2015-06-01 13:43:47 -04:00

batch_drc.log

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

batch_drc.log,1

Changed DS1023 from soic to soicw

2015-06-01 13:43:47 -04:00

batch_drc.log,2

Changed DS1023 from soic to soicw

2015-06-01 13:43:47 -04:00

batch_drc.log,3

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

bestsave.w

Placed all the rooms

2015-03-09 14:40:42 -04:00

BSTPLC.brd

Began arranging fault_detection parts

2015-04-16 20:12:10 -04:00

BSTPLC.brd,1

Began arranging fault_detection parts

2015-04-16 20:12:10 -04:00

caen_buf_mod_v1.mdd

Replicated CAEN_BUF

2015-03-25 16:56:09 -04:00

caen_buf_mod_v2.mdd

Arranged digital parts of CAEN_ANALOG block

2015-03-27 11:59:56 -04:00

dangling_lines.rpt,1

Made VREFM into a plane. Fixed DRCs and Danglers

2015-05-27 16:00:46 -04:00

dbdoctor.log

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

dbdoctor.log,1

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

dbdoctor.log,2

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

dbdoctor.log,3

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

delete_layer_objects.rpt

Fixed problem with GND_Bot not connecting to GNDs

2015-05-27 16:33:36 -04:00

delete_layer_objects.rpt,1

Fixed problem with GND_Bot not connecting to GNDs

2015-05-27 16:33:36 -04:00

devices.dml

Did (most of) Gt Delays. Changed some parts

2015-02-28 01:58:57 -05:00

dfa_constraints.par

Finished all layout crap. Added Neutrino Atlas

2015-05-31 17:16:36 -04:00

dxf2a.log

Finished all layout crap. Added Neutrino Atlas

2015-05-31 17:16:36 -04:00

dxf2a.log,1

Finished all layout crap. Added Neutrino Atlas

2015-05-31 17:16:36 -04:00

dxf2a.log,2

Finished all layout crap. Added Neutrino Atlas

2015-05-31 17:16:36 -04:00

dxf2a.log,3

Finished all layout crap. Added Neutrino Atlas

2015-05-31 17:16:36 -04:00

eco.txt

Changed 1n5822 package to do201AD

2015-06-04 15:18:08 -04:00

eco.txt,1

Changed 1n5822 package to do201AD

2015-06-04 15:18:08 -04:00

extract.log

Changed DS1023 from soic to soicw

2015-06-01 13:43:47 -04:00

extract.log,1

Changed 1n5822 package to do201AD

2015-06-04 15:18:08 -04:00

extract.log,2

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

extract.log,3

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

extract.txt

Commiting here b/c synching isn't changing layout...needs to be fixed

2015-05-12 19:56:40 -04:00

genfeed.log

Commiting here b/c synching isn't changing layout...needs to be fixed

2015-05-12 19:56:40 -04:00

genfeed.log,1

Commiting here b/c synching isn't changing layout...needs to be fixed

2015-05-12 19:56:40 -04:00

gloss.log

Did and Fixed all dangling net report

2015-05-22 11:46:15 -04:00

interconn.iml

Changed LVPECL pulldwn. Made much art-ty changes

2015-05-21 18:45:00 -04:00

interconn.iml,1

Changed LVPECL pulldwn. Made much art-ty changes

2015-05-21 18:45:00 -04:00

load_photoplot.log

Added a note for d6r10 push button

2015-06-08 16:53:59 -04:00

load_photoplot.log,1

Added a note for d6r10 push button

2015-06-08 16:53:59 -04:00

load_photoplot.log,2

Added a note for d6r10 push button

2015-06-08 16:53:59 -04:00

load_photoplot.log,3

Added a note for d6r10 push button

2015-06-08 16:53:59 -04:00

marzece_TUBII_6_5_BOTTOM_Production.art

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

marzece_TUBII_6_5_Drill_Production.art

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

marzece_TUBII_6_5_GND_BOT_Production.art

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

marzece_TUBII_6_5_GND_TOP_Production.art

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

marzece_TUBII_6_5_SilkScreen_Bottom_Production.art

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

marzece_TUBII_6_5_SilkScreen_Top_Production.art

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

marzece_TUBII_6_5_SolderMask_Bottom_Production.art

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

marzece_TUBII_6_5_SolderMask_Top_Production.art

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

marzece_TUBII_6_5_TOP_Production.art

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

marzece_TUBII_6_5_VCC_Production.art

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

marzece_TUBII_6_5_VEE_Production.art

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

marzece_TUBII_6_5_VPM15_Production.art

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

marzece_TUBII_6_5_VTT_Production.art

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

marzece_TubiiPCB_prod-1-8.drl

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

marzece_TubiiPCB_prod-1-8.drl,1

Fixed DS1023 package.

2015-06-02 11:32:17 -04:00

master.tag

Commiting here b/c synching isn't changing layout...needs to be fixed

2015-05-12 19:56:40 -04:00

monitor.sts

Routed the last route

2015-04-23 11:29:06 -04:00

myfavorites.txt

Improved readability and added mounting holes

2015-05-03 19:09:48 -04:00

myfavorites.txt,1

Improved readability and added mounting holes

2015-05-03 19:09:48 -04:00

nc_param.txt

Changed DS1023 from soic to soicw

2015-06-01 13:43:47 -04:00

nc_param.txt,1

Changed DS1023 from soic to soicw

2015-06-01 13:43:47 -04:00

ncdrill.log

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

ncdrill.log,1

Changed 1n5822 package to do201AD

2015-06-04 15:18:08 -04:00

ncdrill.log,2

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

ncdrill.log,3

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

nclegend.log

Added a note for d6r10 push button

2015-06-08 16:53:59 -04:00

nclegend.log,1

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

nclegend.log,2

Added a note for d6r10 push button

2015-06-08 16:53:59 -04:00

nclegend.log,3

Added a note for d6r10 push button

2015-06-08 16:53:59 -04:00

netlist.txt

Used josh's script to look for missing Rs. None found

2015-05-22 19:18:43 -04:00

netrev.lst

Changed 1n5822 package to do201AD

2015-06-04 15:18:08 -04:00

OpenGLInfo.log

Added voids on all planes for THS3062

2015-05-11 17:10:37 -04:00

perf_advisor.log

Changed via-line spacing to 10 mils and fixed DRCs

2015-05-19 19:36:46 -04:00

perf_advisor.log,1

Changed line spacing DRCs...started fixing

2015-05-19 20:05:36 -04:00

perf_advisor.log,2

Changed via-line spacing to 10 mils and fixed DRCs

2015-05-19 19:36:46 -04:00

perf_advisor.log,3

Changed via-line spacing to 10 mils and fixed DRCs

2015-05-19 19:36:46 -04:00

photoplot.log

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

photoplot.log,1

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

photoplot.log,2

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

photoplot.log,3

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

place_txt.txt

Expanded board by 0.2 inches vertically. Doing manufacture prep

2015-05-20 13:59:39 -04:00

place.log

Began arranging fault_detection parts

2015-04-16 20:12:10 -04:00

place.log,1

Began arranging fault_detection parts

2015-04-16 20:12:10 -04:00

place.log,2

Began arranging fault_detection parts

2015-04-16 20:12:10 -04:00

place.log,3

Began arranging fault_detection parts

2015-04-16 20:12:10 -04:00

plctxt.log

Expanded board by 0.2 inches vertically. Doing manufacture prep

2015-05-20 13:59:39 -04:00

pstcmdb2.dat

Changed 1n5822 package to do201AD

2015-06-04 15:18:08 -04:00

quickplace.log

Routing loose ends...nearly done

2015-04-23 04:41:37 -04:00

quickplace.log,1

Routing loose ends...nearly done

2015-04-23 04:41:37 -04:00

quickplace.log,2

Routing loose ends...nearly done

2015-04-23 04:41:37 -04:00

quickplace.log,3

Routing loose ends...nearly done

2015-04-23 04:41:37 -04:00

rename.log

Changed DS1023 from soic to soicw

2015-06-01 13:43:47 -04:00

router.log

Did and Fixed all dangling net report

2015-05-22 11:46:15 -04:00

signoise.log

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

signoise.log,1

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

signoise.log,2

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

signoise.log,3

Remade artwork (which I sent to the PCB company)

2015-06-05 11:17:39 -04:00

specctra.did

Routed the last route

2015-04-23 11:29:06 -04:00

specctra.did,1

Routed the last route

2015-04-23 11:29:06 -04:00

specctra.log

Routed the last route

2015-04-23 11:29:06 -04:00

specctra.log,1

Routed the last route

2015-04-23 11:29:06 -04:00

specctra.log,2

Routed the last route

2015-04-23 11:29:06 -04:00

specctra.log,3

Routed the last route

2015-04-23 11:29:06 -04:00

Tubii_DFA.dfa

Many changes. Added 74lv07a to caen anal stuff

2015-05-26 17:34:42 -04:00

TubiiPCB_prod-1-7-1-7.drl

Added connects to unconnected GNDs & PWRs

2015-05-22 14:42:27 -04:00

TubiiPCB_prod-1-8.drl

Changed DS1023 from soic to soicw

2015-06-01 13:43:47 -04:00

TubiiPCB_test-1-7-1-8.drl

Changed DS1023 from soic to soicw

2015-06-01 13:43:47 -04:00

TubiiPCB_test-1-7.drl

Changed LVPECL pulldwn. Made much art-ty changes

2015-05-21 18:45:00 -04:00

TubiiPCB_V1.brd

Finshed off LO_Gen and did minor routing

2015-02-28 18:43:30 -05:00

TubiiPCB_V2_forget.do

Did layout for gen_delays and pulse_inv

2015-03-08 17:59:06 -04:00

TubiiPCB_V2_rules.do

Did layout for gen_delays and pulse_inv

2015-03-08 17:59:06 -04:00

TubiiPCB_V2.brd

Did layout for gen_delays and pulse_inv

2015-03-08 17:59:06 -04:00

TubiiPCB_V2.dsn

Did layout for gen_delays and pulse_inv

2015-03-08 17:59:06 -04:00

TubiiPCB_V3.brd

Added voids on all planes for THS3062

2015-05-11 17:10:37 -04:00

TubiiPCB_V3.SAV

Added voids on all planes for THS3062

2015-05-11 17:10:37 -04:00

TubiiPCB_V4.brd

Did routing for vcc15/vcc15m

2015-05-11 19:51:47 -04:00

TubiiPCB_V4.SAV

Finshed 15v planes and 3.3v one.

2015-05-12 16:16:08 -04:00

TubiiPCB_V5.brd

Commiting here b/c synching isn't changing layout...needs to be fixed

2015-05-12 19:56:40 -04:00

TubiiPCB_V6.brd

Bookkeeping update, no real changes

2015-09-07 11:41:52 -04:00

TubiiPCB_V6.brd.lck

Bookkeeping update, no real changes

2015-09-07 11:41:52 -04:00

TubiiPCB_V6.SAV

Changed via-line spacing to 10 mils and fixed DRCs

2015-05-19 19:36:46 -04:00

window_drc.log

Changed via-line spacing to 10 mils and fixed DRCs

2015-05-19 19:36:46 -04:00

window_drc.log,1

Changed via-line spacing to 10 mils and fixed DRCs

2015-05-19 19:36:46 -04:00

window_drc.log,2

Changed via-line spacing to 10 mils and fixed DRCs

2015-05-19 19:36:46 -04:00

window_drc.log,3

Changed via-line spacing to 10 mils and fixed DRCs

2015-05-19 19:36:46 -04:00

xsectionChart.log

Expanded board by 0.2 inches vertically. Doing manufacture prep

2015-05-20 13:59:39 -04:00

xsectionChart.log,1

Expanded board by 0.2 inches vertically. Doing manufacture prep

2015-05-20 13:59:39 -04:00

xsectionChart.log,2

Fixed reed relay pins. Created Gerbers

2015-05-20 17:49:41 -04:00

xsectionChart.log,3

Fixed reed relay pins. Created Gerbers

2015-05-20 17:49:41 -04:00

xsectionChartParams.txt

Fixed reed relay pins. Created Gerbers

2015-05-20 17:49:41 -04:00