Tubii_Tk2/worklib/tubii/physical/netrev.lst
2015-06-04 15:18:08 -04:00

107 lines
4.0 KiB
Plaintext

(---------------------------------------------------------------------)
( )
( Allegro Netrev Import Logic )
( )
( Drawing : TubiiPCB_V6.brd )
( Software Version : 16.6P004 )
( Date/Time : Thu Jun 04 15:11:10 2015 )
( )
(---------------------------------------------------------------------)
------ Directives ------
RIPUP_ETCH FALSE;
RIPUP_DELETE_FIRST_SEGMENT FALSE;
RIPUP_RETAIN_BONDWIRE FALSE;
RIPUP_SYMBOLS ALWAYS;
Missing symbol has error FALSE;
SCHEMATIC_DIRECTORY 'C:\Users\QGPWindowsVB\Documents\ANUSTART\worklib\tubii\packaged';
BOARD_DIRECTORY '';
OLD_BOARD_NAME 'C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical/TubiiPCB_V6.brd';
NEW_BOARD_NAME 'C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical/TubiiPCB_V6.brd';
CmdLine: netrev -proj C:\Users\QGPWindowsVB\Documents\ANUSTART\tubii_tk2.cpm -y 1 -O C:\Users\QGPWindowsVB\Documents\ANUSTART\worklib\tubii\physical\TubiiPCB_V6.brd C:\Users\QGPWindowsVB\Documents\ANUSTART\worklib\tubii\physical\TubiiPCB_V6.brd -$
------ Preparing to read pst files ------
Starting to read C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/packaged/pstchip.dat
Finished reading C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/packaged/pstchip.dat (00:00:01.42)
Starting to read C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/packaged/pstxprt.dat
Finished reading C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/packaged/pstxprt.dat (00:00:00.17)
Starting to read C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/packaged/pstxnet.dat
Finished reading C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/packaged/pstxnet.dat (00:00:00.18)
------ Oversights/Warnings/Errors ------
===========================================================
Start Constraint Diff3 Import
Constraint File: C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/packaged/pstcmdb.dat
Allegro Baseline: C:/Users/QGPWIN~1/AppData/Local/Temp/#Taaaaae00340.tmp
Start time: Thu Jun 04 15:11:13 2015
===========================================================
===========================================================
Finished Constraint Update Time: Thu Jun 04 15:11:16 2015
===========================================================
------ Library Paths ------
MODULEPATH = .
C:/Cadence/SPB_16.6/share/local/pcb/modules
PSMPATH = .
symbols
..
../symbols
C:/Cadence/SPB_16.6/share/local/pcb/symbols
C:/Cadence/SPB_16.6/share/pcb/pcb_lib/symbols
C:/Cadence/SPB_16.6/share/pcb/allegrolib/symbols
PADPATH = .
symbols
..
../symbols
C:/Cadence/SPB_16.6/share/local/pcb/padstacks
C:/Cadence/SPB_16.6/share/pcb/pcb_lib/symbols
C:/Cadence/SPB_16.6/share/pcb/allegrolib/symbols
------ Summary Statistics ------
netrev run on Jun 4 15:11:09 2015
DESIGN NAME : 'TUBII'
PACKAGING ON 04-Jun-2015 AT 15:06:54
COMPILE 'logic'
CHECK_PIN_NAMES OFF
CROSS_REFERENCE OFF
DIRECTORIES <none>
FEEDBACK OFF
INCREMENTAL OFF
INTERFACE_TYPE PHYSICAL
LIBRARIES 'tubii_tk2_lib' 'standard' 'diode' 'dig_ecl' 'opa' 'opamp'
'special' 'capacitors' 'diodes' 'ecl' 'physparts' 'regulators'
'resistors' 'SNO_standard' 'ttl' 'misc' 'transistors'
MASTER_LIBRARIES <none>
MAX_ERRORS 500
MERGE_MINIMUM 5
NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
NET_NAME_LENGTH 24
OVERSIGHTS ON
REPLACE_CHECK OFF
SINGLE_NODE_NETS ON
SPLIT_MINIMUM 0
SUPPRESS 20
WARNINGS ON
No error detected
No oversight detected
No warning detected
cpu time 0:22:31
elapsed time 0:00:12