107 lines
4.0 KiB
Plaintext
107 lines
4.0 KiB
Plaintext
(---------------------------------------------------------------------)
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( )
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( Allegro Netrev Import Logic )
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( )
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( Drawing : TubiiPCB_V6.brd )
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( Software Version : 16.6P004 )
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( Date/Time : Thu Jun 04 15:11:10 2015 )
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( )
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(---------------------------------------------------------------------)
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------ Directives ------
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RIPUP_ETCH FALSE;
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RIPUP_DELETE_FIRST_SEGMENT FALSE;
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RIPUP_RETAIN_BONDWIRE FALSE;
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RIPUP_SYMBOLS ALWAYS;
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Missing symbol has error FALSE;
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SCHEMATIC_DIRECTORY 'C:\Users\QGPWindowsVB\Documents\ANUSTART\worklib\tubii\packaged';
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BOARD_DIRECTORY '';
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OLD_BOARD_NAME 'C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical/TubiiPCB_V6.brd';
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NEW_BOARD_NAME 'C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical/TubiiPCB_V6.brd';
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CmdLine: netrev -proj C:\Users\QGPWindowsVB\Documents\ANUSTART\tubii_tk2.cpm -y 1 -O C:\Users\QGPWindowsVB\Documents\ANUSTART\worklib\tubii\physical\TubiiPCB_V6.brd C:\Users\QGPWindowsVB\Documents\ANUSTART\worklib\tubii\physical\TubiiPCB_V6.brd -$
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------ Preparing to read pst files ------
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Starting to read C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/packaged/pstchip.dat
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Finished reading C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/packaged/pstchip.dat (00:00:01.42)
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Starting to read C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/packaged/pstxprt.dat
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Finished reading C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/packaged/pstxprt.dat (00:00:00.17)
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Starting to read C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/packaged/pstxnet.dat
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Finished reading C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/packaged/pstxnet.dat (00:00:00.18)
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------ Oversights/Warnings/Errors ------
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===========================================================
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Start Constraint Diff3 Import
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Constraint File: C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/packaged/pstcmdb.dat
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Allegro Baseline: C:/Users/QGPWIN~1/AppData/Local/Temp/#Taaaaae00340.tmp
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Start time: Thu Jun 04 15:11:13 2015
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===========================================================
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===========================================================
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Finished Constraint Update Time: Thu Jun 04 15:11:16 2015
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===========================================================
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------ Library Paths ------
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MODULEPATH = .
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C:/Cadence/SPB_16.6/share/local/pcb/modules
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PSMPATH = .
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symbols
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..
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../symbols
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C:/Cadence/SPB_16.6/share/local/pcb/symbols
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C:/Cadence/SPB_16.6/share/pcb/pcb_lib/symbols
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C:/Cadence/SPB_16.6/share/pcb/allegrolib/symbols
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PADPATH = .
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symbols
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..
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../symbols
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C:/Cadence/SPB_16.6/share/local/pcb/padstacks
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C:/Cadence/SPB_16.6/share/pcb/pcb_lib/symbols
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C:/Cadence/SPB_16.6/share/pcb/allegrolib/symbols
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------ Summary Statistics ------
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netrev run on Jun 4 15:11:09 2015
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DESIGN NAME : 'TUBII'
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PACKAGING ON 04-Jun-2015 AT 15:06:54
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COMPILE 'logic'
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CHECK_PIN_NAMES OFF
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CROSS_REFERENCE OFF
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DIRECTORIES <none>
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FEEDBACK OFF
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INCREMENTAL OFF
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INTERFACE_TYPE PHYSICAL
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LIBRARIES 'tubii_tk2_lib' 'standard' 'diode' 'dig_ecl' 'opa' 'opamp'
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'special' 'capacitors' 'diodes' 'ecl' 'physparts' 'regulators'
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'resistors' 'SNO_standard' 'ttl' 'misc' 'transistors'
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MASTER_LIBRARIES <none>
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MAX_ERRORS 500
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MERGE_MINIMUM 5
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NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
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NET_NAME_LENGTH 24
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OVERSIGHTS ON
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REPLACE_CHECK OFF
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SINGLE_NODE_NETS ON
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SPLIT_MINIMUM 0
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SUPPRESS 20
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WARNINGS ON
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No error detected
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No oversight detected
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No warning detected
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cpu time 0:22:31
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elapsed time 0:00:12
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