575 lines
30 KiB
Plaintext
575 lines
30 KiB
Plaintext
#
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# ===============================================================================
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# Allegro PCB Router
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# Copyright 1990-2010 Cadence Design Systems, Inc. All Rights Reserved.
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# ===============================================================================
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#
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# Software licensed for sale by Cadence Design Systems, Inc.
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# Current time = Mon Mar 09 12:37:57 2015
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#
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# Allegro PCB Router v16-6-112 made 2012/09/12 at 23:00:45
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# Running on: qgpwindowsvb-pc, OS Version: WindowsNT 6.1.7601, Architecture: Intel Pentium II, III, or 4
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# Licensing: The program will not obey any unlicensed rules
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# No graphics will be displayed.
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# Design Name C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
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# Batch File Name: pasde.do
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# Did File Name: C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical/specctra.did
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# Current time = Mon Mar 09 12:37:58 2015
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# PCB C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical
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# Master Unit set up as: MIL 100
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# PCB Limits xlo= 40.0000 ylo=-920.0000 xhi=16760.0000 yhi=16560.0000
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# Total 222 Images Consolidated.
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# Via VIA z=1, 2 xlo=-12.0000 ylo=-12.0000 xhi= 12.0000 yhi= 12.0000
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#
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# VIA TOP BOTTOM
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#
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# TOP ------ VIA
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# BOTTOM VIA ------
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#
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# <<WARNING:>> The * character appears in a net name.
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# * has been disabled as a wildcard character for nets.
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# You can use the wildcard command to change the wildcard character.
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# <<WARNING:>> Net GND is defined as a signal net and contains 436 pins.
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# This is more pins than most signal nets contain.
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# Please verify whether net GND should be a signal net or a power net.
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# Note that a signal net will be routed as starburst or daisy chain.
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# Wires Processed 461, Vias Processed 163
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# Using colormap in design file.
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# Layers Processed: Signal Layers 2
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# Layers Processed: Power Layers 5
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# Components Placed 881, Images Processed 268, Padstacks Processed 23
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# Nets Processed 677, Net Terminals 2876
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# PCB Area=231040000.000 EIC=240 Area/EIC=962666.667 SMDs=611
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# Total Pin Count: 3371
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# Signal Connections Created 1405
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#
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# Design Rules --------------------------------------------
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# Via Grid 0.1000 with offset 0.0000
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# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
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# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
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# Cpu Time = 0:00:00 Elapsed Time = 0:00:00
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#
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# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
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# Nets 677 Connections 2013 Unroutes 1741
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# Signal Layers 2 Power Layers 5
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# Wire Junctions 79, at vias 37 Total Vias 163
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# Percent Connected 11.13
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# Manhattan Length 5601601.2000 Horizontal 1714290.3500 Vertical 3887310.8500
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# Routed Length 125587.1949 Horizontal 69487.4000 Vertical 67884.5000
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# Ratio Actual / Manhattan 0.0224
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# Unconnected Length 5499673.1000 Horizontal 1667309.8000 Vertical 3832363.3000
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# Total Conflicts: 159 (Cross: 2, Clear: 157, Xtalk: 0, Length: 0, Polygon Clear: 0 )
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# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
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# Loading Do File pasde.do ...
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# Loading Do File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC_rules.do ...
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# Nets UNNAMED_1_FRONTPORTS_I2_SYNCP and UNNAMED_1_FRONTPORTS_I2_SYNCN have been defined as a balanced pair.
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# Nets CLK_BAD_P and CLK_BAD_N have been defined as a balanced pair.
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# <<WARNING:>> Could not form pair of nets DEF_CLK_DIV8_P and DEF_CLK_DIV8_N.
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# <<WARNING:>> Could not form pair of nets UNNAMED_1_FRONTPORTS_I2_MTCAM_4 and UNNAMED_1_FRONTPORTS_I2_MTCAM_3.
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# <<WARNING:>> Could not form pair of nets UNNAMED_1_FRONTPORTS_I2_MTCAM_1 and UNNAMED_1_FRONTPORTS_I2_MTCAMIM.
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# <<WARNING:>> Could not form pair of nets UNNAMED_1_FRONTPORTS_I2_RIBBO_3 and UNNAMED_1_FRONTPORTS_I2_RIBBO_2.
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# Nets UNNAMED_1_MC10E116_I4_Q3_1 and UNNAMED_1_MC10E116_I4_Q3 have been defined as a balanced pair.
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# <<WARNING:>> Could not form pair of nets DEF_CLK_DIV4_P and DEF_CLK_DIV4_N.
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# Nets UNNAMED_1_CAENCOMS_I8_GT2P and GT2_N have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I4_Q2_1 and UNNAMED_1_MC10E116_I4_Q2 have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I3_Q3_1 and UNNAMED_1_MC10E116_I3_Q3 have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I4_Q1_1 and UNNAMED_1_MC10E116_I4_Q1 have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I3_Q2_1 and UNNAMED_1_MC10E116_I3_Q2 have been defined as a balanced pair.
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# <<WARNING:>> Could not form pair of nets DEF_CLK_DIV2_P and DEF_CLK_DIV2_N.
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# Nets UNNAMED_1_MC10E116_I4_Q0_1 and UNNAMED_1_MC10E116_I4_Q0 have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I3_Q1_1 and UNNAMED_1_MC10E116_I3_Q1 have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I1_Q3_1 and UNNAMED_1_MC10E116_I1_Q3 have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I3_Q0_1 and UNNAMED_1_MC10E116_I3_Q0 have been defined as a balanced pair.
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# Nets CHOSEN_CLK_P and CHOSEN_CLK_N have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I1_Q0_1 and UNNAMED_1_MC10E116_I1_Q0 have been defined as a balanced pair.
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# Nets UNNAMED_1_CHANGECLKS_I3_CHANG_1 and UNNAMED_1_CHANGECLKS_I3_CHANGEC have been defined as a balanced pair.
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# Nets USE_BCKP_P and USE_BCKP_N have been defined as a balanced pair.
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# Nets TRIG_GATE2_P and TRIG_GATE2_N have been defined as a balanced pair.
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# Nets UNNAMED_1_FRONTPORTS_I2_SYNC24P and UNNAMED_1_FRONTPORTS_I2_SYNC24N have been defined as a balanced pair.
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# Nets TRIG_GATE1_P and TRIG_GATE1_N have been defined as a balanced pair.
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# Nets UNNAMED_1_FRONTPORTS_I2_GTP and UNNAMED_1_FRONTPORTS_I2_GTN have been defined as a balanced pair.
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# Nets BCKP_CLK_BUFD_P and BCKP_CLK_BUFD_N have been defined as a balanced pair.
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# Nets USE_DEFAULT_P and USE_DEFAULT_N have been defined as a balanced pair.
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# Nets SYNC_2_P and SYNC_2_N have been defined as a balanced pair.
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# Nets TELLIE_DELAY_BUF_P and TELLIE_DELAY_BUF_N have been defined as a balanced pair.
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# Nets UNNAMED_1_AD96687_I1_Q2_1 and UNNAMED_1_AD96687_I1_Q2 have been defined as a balanced pair.
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# Nets UNNAMED_1_AD96687_I1_Q1_1 and UNNAMED_1_AD96687_I1_Q1 have been defined as a balanced pair.
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# Nets RIB10_P and RIB10_N have been defined as a balanced pair.
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# Nets UNNAMED_1_DEFAULTCLKSEL_I1_BCKP and UNNAMED_1_MC10E116_I1_D0 have been defined as a balanced pair.
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# <<WARNING:>> Could not form pair of nets UNNAMED_1_FRONTPORTS_I2_SYNCL_1 and UNNAMED_1_FRONTPORTS_I2_SYNCLVD.
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# Nets SYNC24_2_P and SYNC24_2_N have been defined as a balanced pair.
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# <<WARNING:>> Could not form pair of nets UNNAMED_1_FRONTPORTS_I2_CLK100P and UNNAMED_1_FRONTPORTS_I2_CLK100N.
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# Nets UNNAMED_1_MC10E116_I22_Q1_1 and UNNAMED_1_MC10E116_I22_Q1 have been defined as a balanced pair.
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# Nets CHOSEN_CLK2_P and CHOSEN_CLK2_N have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I22_Q0_1 and UNNAMED_1_MC10E116_I22_Q0 have been defined as a balanced pair.
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# Nets UNNAMED_1_CHANGECLKS_I3_BCKPC_3 and UNNAMED_1_CHANGECLKS_I3_BCKPC_2 have been defined as a balanced pair.
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# Nets UNNAMED_1_CHANGECLKS_I3_BCKPC_1 and UNNAMED_1_CHANGECLKS_I3_BCKPCLK have been defined as a balanced pair.
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# <<WARNING:>> Could not form pair of nets UNNAMED_1_FRONTPORTS_I2_SYNC2_1 and UNNAMED_1_FRONTPORTS_I2_SYNC24L.
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# Nets UNNAMED_1_FRONTPORTS_I2_RIBBO_1 and UNNAMED_1_FRONTPORTS_I2_RIBBONP have been defined as a balanced pair.
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# Nets RIB9_P and RIB9_N have been defined as a balanced pair.
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# Nets RIB8_P and RIB8_N have been defined as a balanced pair.
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# Nets RIB7_P and RIB7_N have been defined as a balanced pair.
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# Nets RIB6_P and RIB6_N have been defined as a balanced pair.
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# Nets UNNAMED_1_CSMD0805_I70_B and UNNAMED_1_CSMD0805_I64_B have been defined as a balanced pair.
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# Nets RIB5_P and RIB5_N have been defined as a balanced pair.
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# Nets RIB4_P and RIB4_N have been defined as a balanced pair.
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# Nets RIB3_P and RIB3_N have been defined as a balanced pair.
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# Nets RIB2_P and RIB2_N have been defined as a balanced pair.
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# Nets RIB1_P and RIB1_N have been defined as a balanced pair.
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# <<WARNING:>> Could not form pair of nets UNNAMED_1_FRONTPORTS_I2_EXTT<4> and UNNAMED_1_CSMD0603_I55_A.
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# <<WARNING:>> Could not form pair of nets UNNAMED_1_FRONTPORTS_I2_EXTT<0> and UNNAMED_1_CSMD0603_I54_B.
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# Nets SMELLIE_DELAY_BUF_P and SMELLIE_DELAY_BUF_N have been defined as a balanced pair.
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# Nets CHANGE_CLK2_P and CHANGE_CLK2_N have been defined as a balanced pair.
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# <<WARNING:>> Could not form pair of nets UNNAMED_1_FRONTPORTS_I2_LOSTA_1 and UNNAMED_1_FRONTPORTS_I2_LOSTARO.
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# <<WARNING:>> Could not form pair of nets DEF_CLK_DIVD_P and DEF_CLK_DIVD_N.
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# Nets TRIG_PULS2_P and TRIG_PULS2_N have been defined as a balanced pair.
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# <<WARNING:>> Could not form pair of nets UNNAMED_1_FRONTPORTS_I2_SMELLIE and UNNAMED_1_CSMD0603_I10_B_1.
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# Nets TRIG_PULS1_P and TRIG_PULS1_N have been defined as a balanced pair.
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# Nets UNNAMED_1_FRONTPORTS_I2_ECLTOLV and VBB_TRANS have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I2_D0 and LO_STAR_RAW have been defined as a balanced pair.
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# Nets UNNAMED_1_CHANGECLKS_I3_DEFAU_1 and UNNAMED_1_CHANGECLKS_I3_DEFAULT have been defined as a balanced pair.
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# Colormap Written to File _notify.std
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# Enter command <# Loading Do File C:/Users/QGPWIN~1/AppData/Local/Temp/#Taaaaal02200.tmp ...
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# All Components Unselected.
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# All Nets Unselected.
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# Component U44 Selected.
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# Component U42 Selected.
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# Component U41 Selected.
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# Component U43 Selected.
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# Component U40 Selected.
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# Component U39 Selected.
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# Component U4 Selected.
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# Component U46 Selected.
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# Component U45 Selected.
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# Component U47 Selected.
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set route_diagonal 4
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grid wire 0.100000 (direction x) (offset 0.000000)
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grid wire 0.100000 (direction y) (offset 0.000000)
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grid via 0.100000 (direction x) (offset 0.000000)
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grid via 0.100000 (direction y) (offset 0.000000)
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protect all wires
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# All Wires Protected.
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direction TOP horizontal
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select layer TOP
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unprotect layer_wires TOP
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# Wires on layer TOP were Unprotected.
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direction BOTTOM vertical
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select layer BOTTOM
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unprotect layer_wires BOTTOM
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# Wires on layer BOTTOM were Unprotected.
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cost via -1
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# System default cost will be used.
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set turbo_stagger off
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limit outside -1
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rule pcb (patterns_allowed trombone accordion)
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set pattern_stacking on
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rule pcb (sawtooth_amplitude -1 -1)
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rule pcb (sawtooth_gap -1)
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rule pcb (accordion_amplitude -1 -1)
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rule pcb (accordion_gap -1)
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rule pcb (trombone_run_length -1)
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rule pcb (trombone_gap -1)
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unprotect selected
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# All Selected Wires Unprotected.
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smart_route (auto_fanout off) (auto_testpoint off) (auto_miter on)
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# Smart Route: Only part of the wires are selected for routing.
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# Using modified smart_route algorithm.
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# Smart Route: Executing 50 route passes.
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# Current time = Mon Mar 09 12:39:20 2015
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#
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# VIA TOP BOTTOM
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#
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# TOP ------ VIA
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# BOTTOM VIA ------
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#
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#
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# Design Rules --------------------------------------------
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# Via Grid 0.1000 with offset 0.0000
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# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
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# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
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#
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# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
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# Nets 677 Connections 2013 Unroutes 1741
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# Signal Layers 2 Power Layers 5
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# Wire Junctions 79, at vias 36 Total Vias 163
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# Percent Connected 11.23
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# Manhattan Length 5634595.1000 Horizontal 1723947.6500 Vertical 3910647.4500
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# Routed Length 125587.1949 Horizontal 69487.4000 Vertical 67884.5000
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# Ratio Actual / Manhattan 0.0223
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# Unconnected Length 5534071.2000 Horizontal 1674474.3000 Vertical 3859596.9000
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# 0 bend points have been removed.
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# Attempts 118 Successes 115 Failures 3 Vias 287
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# 0 bend points have been removed.
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# Attempts 2 Successes 0 Failures 2 Vias 287
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# 0 bend points have been removed.
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# 0 bend points have been removed.
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# 0 bend points have been removed.
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# 0 bend points have been removed.
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# Start Route Pass 1 of 50
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# Routing 113 wires.
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# Total Conflicts: 11 (Cross: 6, Clear: 5, Xtalk: 0, Length: 0, Polygon Clear: 0 )
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# Total Unroutes: 1619
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# Attempts 104 Successes 103 Failures 1 Vias 317
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# Cpu Time = 0:00:07 Elapsed Time = 0:00:09
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# End Pass 1 of 50
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# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
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# <<WARNING:>> Smart Route: Unroute count 1741 is very high after 1 passes.
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# Design may not reach 100%.
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# Check placement, components outside boundary, design rules, keepout positions
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# Start Route Pass 2 of 50
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# Routing 25 wires.
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# 1 bend points have been removed.
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# 0 bend points have been removed.
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# 6 bend points have been removed.
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# Total Conflicts: 24 (Cross: 9, Clear: 15, Xtalk: 0, Length: 0, Polygon Clear: 0 )
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# Total Unroutes: 1618
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# Attempts 20 Successes 20 Failures 0 Vias 314
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# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
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# End Pass 2 of 50
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# <<WARNING:>> Smart Route: Conflict reduction rate 0 is very low
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# after 2 passes.
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# Design may not reach 100%.
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# Check number of layers, grids and design rules.
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# Start Route Pass 3 of 50
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# Routing 24 wires.
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# 2 bend points have been removed.
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# 0 bend points have been removed.
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# 3 bend points have been removed.
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# Total Conflicts: 18 (Cross: 7, Clear: 11, Xtalk: 0, Length: 0, Polygon Clear: 0 )
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# Total Unroutes: 1618
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# Attempts 15 Successes 15 Failures 0 Vias 315
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# Cpu Time = 0:00:03 Elapsed Time = 0:00:04
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# End Pass 3 of 50
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# <<WARNING:>> Smart Route: Average reduction ratio only 13 after 3 passes.
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# Design may converge very slowly.
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# Monitor status file carefully.
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# Start Route Pass 4 of 50
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# Routing 17 wires.
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# 0 bend points have been removed.
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# 0 bend points have been removed.
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# 3 bend points have been removed.
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# Total Conflicts: 18 (Cross: 5, Clear: 13, Xtalk: 0, Length: 0, Polygon Clear: 0 )
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# Total Unroutes: 1618
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# Attempts 12 Successes 12 Failures 0 Vias 318
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# Cpu Time = 0:00:03 Elapsed Time = 0:00:03
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# End Pass 4 of 50
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# <<WARNING:>> Smart Route: Average reduction ratio only 8 after 4 passes.
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# Design may converge very slowly.
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# Monitor status file carefully.
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# Start Route Pass 5 of 50
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# Routing 20 wires.
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# 0 bend points have been removed.
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# 0 bend points have been removed.
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# 4 bend points have been removed.
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# Total Conflicts: 5 (Cross: 3, Clear: 2, Xtalk: 0, Length: 0, Polygon Clear: 0 )
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# Total Unroutes: 1618
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# Attempts 9 Successes 9 Failures 0 Vias 314
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# Cpu Time = 0:00:02 Elapsed Time = 0:00:03
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# End Pass 5 of 50
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# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
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# <<WARNING:>> Smart Route: Average reduction ratio only 24 after 5 passes.
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# Design may converge very slowly.
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# Monitor status file carefully.
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# Start Route Pass 6 of 50
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# Routing 8 wires.
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# Total Conflicts: 5 (Cross: 3, Clear: 2, Xtalk: 0, Length: 0, Polygon Clear: 0 )
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# Total Unroutes: 1618
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# Attempts 4 Successes 4 Failures 0 Vias 314
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# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
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# End Pass 6 of 50
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# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
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# Smart Route: Smart_route progressing normally after 6 passes.
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# Start Route Pass 7 of 50
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# Routing 8 wires.
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# Total Conflicts: 5 (Cross: 3, Clear: 2, Xtalk: 0, Length: 0, Polygon Clear: 0 )
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# Total Unroutes: 1618
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# Attempts 2 Successes 2 Failures 0 Vias 314
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# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
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# End Pass 7 of 50
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# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
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# Smart Route: Smart_route progressing normally after 7 passes.
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# Start Route Pass 8 of 50
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# Routing 7 wires.
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# Total Conflicts: 5 (Cross: 3, Clear: 2, Xtalk: 0, Length: 0, Polygon Clear: 0 )
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# Total Unroutes: 1618
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# Attempts 3 Successes 3 Failures 0 Vias 314
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# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
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# End Pass 8 of 50
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# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
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# Smart Route: Smart_route progressing normally after 8 passes.
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# Start Route Pass 9 of 50
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# Routing 7 wires.
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# Total Conflicts: 5 (Cross: 3, Clear: 2, Xtalk: 0, Length: 0, Polygon Clear: 0 )
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# Total Unroutes: 1618
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# Attempts 2 Successes 2 Failures 0 Vias 314
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# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
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# End Pass 9 of 50
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# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
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# Smart Route: Smart_route progressing normally after 9 passes.
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# Start Route Pass 10 of 50
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# Routing 7 wires.
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# 0 bend points have been removed.
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# 0 bend points have been removed.
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# 3 bend points have been removed.
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# Total Conflicts: 5 (Cross: 3, Clear: 2, Xtalk: 0, Length: 0, Polygon Clear: 0 )
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# Total Unroutes: 1618
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# Attempts 3 Successes 3 Failures 0 Vias 314
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# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
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# End Pass 10 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 10 passes.
|
||
# Start Route Pass 11 of 50
|
||
# Routing 8 wires.
|
||
# Total Conflicts: 5 (Cross: 3, Clear: 2, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1618
|
||
# Attempts 2 Successes 2 Failures 0 Vias 314
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:02
|
||
# End Pass 11 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 11 passes.
|
||
# Start Route Pass 12 of 50
|
||
# Routing 7 wires.
|
||
# Total Conflicts: 5 (Cross: 3, Clear: 2, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1618
|
||
# Attempts 3 Successes 3 Failures 0 Vias 314
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
|
||
# End Pass 12 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 12 passes.
|
||
# Start Route Pass 13 of 50
|
||
# Routing 8 wires.
|
||
# Total Conflicts: 5 (Cross: 3, Clear: 2, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1618
|
||
# Attempts 2 Successes 2 Failures 0 Vias 314
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
|
||
# End Pass 13 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 13 passes.
|
||
# Start Route Pass 14 of 50
|
||
# Routing 7 wires.
|
||
# Total Conflicts: 5 (Cross: 3, Clear: 2, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1618
|
||
# Attempts 3 Successes 3 Failures 0 Vias 314
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
|
||
# End Pass 14 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 14 passes.
|
||
# Start Route Pass 15 of 50
|
||
# Routing 7 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 3 bend points have been removed.
|
||
# Total Conflicts: 5 (Cross: 3, Clear: 2, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1618
|
||
# Attempts 2 Successes 2 Failures 0 Vias 314
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
|
||
# End Pass 15 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 15 passes.
|
||
# Start Route Pass 16 of 50
|
||
# Routing 7 wires.
|
||
# Total Conflicts: 5 (Cross: 3, Clear: 2, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1618
|
||
# Attempts 3 Successes 3 Failures 0 Vias 314
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
|
||
# End Pass 16 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 16 passes.
|
||
# Start Route Pass 17 of 50
|
||
# Routing 8 wires.
|
||
# Total Conflicts: 5 (Cross: 3, Clear: 2, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1618
|
||
# Attempts 2 Successes 2 Failures 0 Vias 314
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
|
||
# End Pass 17 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 17 passes.
|
||
# Start Route Pass 18 of 50
|
||
# Routing 7 wires.
|
||
# Total Conflicts: 5 (Cross: 3, Clear: 2, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1618
|
||
# Attempts 3 Successes 3 Failures 0 Vias 314
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
|
||
# End Pass 18 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 18 passes.
|
||
# Start Route Pass 19 of 50
|
||
# Routing 7 wires.
|
||
# Total Conflicts: 5 (Cross: 3, Clear: 2, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1618
|
||
# Attempts 2 Successes 2 Failures 0 Vias 314
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:02
|
||
# End Pass 19 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 19 passes.
|
||
# Start Route Pass 20 of 50
|
||
# Routing 7 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 3 bend points have been removed.
|
||
# Total Conflicts: 5 (Cross: 3, Clear: 2, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1618
|
||
# Attempts 3 Successes 3 Failures 0 Vias 314
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:02
|
||
# End Pass 20 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 20 passes.
|
||
# Start Route Pass 21 of 50
|
||
# Routing 8 wires.
|
||
# Total Conflicts: 5 (Cross: 3, Clear: 2, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1618
|
||
# Attempts 2 Successes 2 Failures 0 Vias 314
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:02
|
||
# End Pass 21 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 21 passes.
|
||
# Start Route Pass 22 of 50
|
||
# Routing 7 wires.
|
||
# Total Conflicts: 5 (Cross: 3, Clear: 2, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1618
|
||
# Attempts 3 Successes 3 Failures 0 Vias 314
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:02
|
||
# End Pass 22 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 22 passes.
|
||
# Start Route Pass 23 of 50
|
||
# Routing 8 wires.
|
||
# Total Conflicts: 5 (Cross: 3, Clear: 2, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1618
|
||
# Attempts 2 Successes 2 Failures 0 Vias 314
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
|
||
# End Pass 23 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 23 passes.
|
||
# Start Route Pass 24 of 50
|
||
# Routing 7 wires.
|
||
# Total Conflicts: 5 (Cross: 3, Clear: 2, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1618
|
||
# Attempts 3 Successes 3 Failures 0 Vias 314
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
|
||
# End Pass 24 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 24 passes.
|
||
# Start Route Pass 25 of 50
|
||
# Routing 8 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 3 bend points have been removed.
|
||
# Total Conflicts: 5 (Cross: 3, Clear: 2, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1618
|
||
# Attempts 2 Successes 2 Failures 0 Vias 314
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:03
|
||
# End Pass 25 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 25 passes.
|
||
# Start Route Pass 26 of 50
|
||
# Routing 7 wires.
|
||
# Total Conflicts: 5 (Cross: 3, Clear: 2, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1618
|
||
# Attempts 3 Successes 3 Failures 0 Vias 314
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:02
|
||
# End Pass 26 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# <<ERROR:>> Smart Route: Design is unroutable, not enough resources.
|
||
# Many unroutes will exist if you use the filter command.
|
||
# Check number of layers, grids, design rules and placement.
|
||
# Cpu Time = 0:01:06 Elapsed Time = 0:01:20
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 6| 5| 1| 1619| 317| 0| 0| 0| 0:00:07| 0:00:07|
|
||
# Route | 2| 9| 15| 0| 1618| 314| 0| 0| 0| 0:00:02| 0:00:09|
|
||
# Route | 3| 7| 11| 0| 1618| 315| 0| 0| 25| 0:00:03| 0:00:12|
|
||
# Route | 4| 5| 13| 0| 1618| 318| 0| 0| 0| 0:00:03| 0:00:15|
|
||
# Route | 5| 3| 2| 0| 1618| 314| 0| 0| 72| 0:00:02| 0:00:17|
|
||
# Route | 6| 3| 2| 0| 1618| 314| 0| 0| 0| 0:00:02| 0:00:19|
|
||
# Route | 7| 3| 2| 0| 1618| 314| 0| 0| 0| 0:00:02| 0:00:21|
|
||
# Route | 8| 3| 2| 0| 1618| 314| 0| 0| 0| 0:00:02| 0:00:23|
|
||
# Route | 9| 3| 2| 0| 1618| 314| 0| 0| 0| 0:00:02| 0:00:25|
|
||
# Route | 10| 3| 2| 0| 1618| 314| 0| 0| 0| 0:00:02| 0:00:27|
|
||
# Route | 11| 3| 2| 0| 1618| 314| 0| 0| 0| 0:00:01| 0:00:28|
|
||
# Route | 12| 3| 2| 0| 1618| 314| 0| 0| 0| 0:00:02| 0:00:30|
|
||
# Route | 13| 3| 2| 0| 1618| 314| 0| 0| 0| 0:00:02| 0:00:32|
|
||
# Route | 14| 3| 2| 0| 1618| 314| 0| 0| 0| 0:00:02| 0:00:34|
|
||
# Route | 15| 3| 2| 0| 1618| 314| 0| 0| 0| 0:00:02| 0:00:36|
|
||
# Route | 16| 3| 2| 0| 1618| 314| 0| 0| 0| 0:00:02| 0:00:38|
|
||
# Route | 17| 3| 2| 0| 1618| 314| 0| 0| 0| 0:00:02| 0:00:40|
|
||
# Route | 18| 3| 2| 0| 1618| 314| 0| 0| 0| 0:00:02| 0:00:42|
|
||
# Route | 19| 3| 2| 0| 1618| 314| 0| 0| 0| 0:00:01| 0:00:43|
|
||
# Route | 20| 3| 2| 0| 1618| 314| 0| 0| 0| 0:00:01| 0:00:44|
|
||
# Route | 21| 3| 2| 0| 1618| 314| 0| 0| 0| 0:00:01| 0:00:45|
|
||
# Route | 22| 3| 2| 0| 1618| 314| 0| 0| 0| 0:00:01| 0:00:46|
|
||
# Route | 23| 3| 2| 0| 1618| 314| 0| 0| 0| 0:00:02| 0:00:48|
|
||
# Route | 24| 3| 2| 0| 1618| 314| 0| 0| 0| 0:00:02| 0:00:50|
|
||
# Route | 25| 3| 2| 0| 1618| 314| 0| 0| 0| 0:00:02| 0:00:52|
|
||
# Route | 26| 3| 2| 0| 1618| 314| 0| 0| 0| 0:00:01| 0:00:53|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:53
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1618
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 146, at vias 87 Total Vias 314
|
||
# Percent Connected 19.37
|
||
# Manhattan Length 5640967.9000 Horizontal 1727849.0600 Vertical 3913118.8400
|
||
# Routed Length 237155.7428 Horizontal 135673.2800 Vertical 120989.8600
|
||
# Ratio Actual / Manhattan 0.0420
|
||
# Unconnected Length 5438871.0000 Horizontal 1619707.6000 Vertical 3819163.4000
|
||
# <<ERROR:>> Smart Route: Smart_route command aborting due to failures.
|
||
write routes (changed_only) (reset_changed) C:/Users/QGPWIN~1/AppData/Local/Temp/#Taaaaam02200.tmp
|
||
# Routing Written to File C:/Users/QGPWIN~1/AppData/Local/Temp/#Taaaaam02200.tmp
|
||
# Loading Do File C:/Users/QGPWIN~1/AppData/Local/Temp/#Taaaaao02200.tmp ...
|
||
# All Components Unselected.
|
||
# All Nets Unselected.
|
||
# Net UNNAMED_1_CAENCOMS_I8_GT2P Selected.
|
||
# All Selected Wires Unprotected.
|
||
# All unprotected selected wires were deleted.
|
||
# Current time = Mon Mar 09 12:41:54 2015
|
||
# Total Conflicts: 5 (Cross: 3, Clear: 2, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:00
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1623
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 140, at vias 82 Total Vias 303
|
||
# Percent Connected 19.13
|
||
# Manhattan Length 5640967.9000 Horizontal 1727849.0600 Vertical 3913118.8400
|
||
# Routed Length 225462.2075 Horizontal 127351.8800 Vertical 116408.7200
|
||
# Ratio Actual / Manhattan 0.0400
|
||
# Unconnected Length 5450396.6000 Horizontal 1627242.6000 Vertical 3823154.0000
|
||
# All Components Unselected.
|
||
# All Nets Unselected.
|
||
# Current time = Mon Mar 09 12:41:54 2015
|
||
# Nets Processed 678, Net Terminals 3768
|
||
# Signal Connections Created 1177
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Total Conflicts: 5 (Cross: 3, Clear: 2, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:01
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 678 Connections 2013 Unroutes 1623
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 150, at vias 90 Total Vias 307
|
||
# Percent Connected 19.13
|
||
# Manhattan Length 5641118.9000 Horizontal 1727939.5600 Vertical 3913179.3400
|
||
# Routed Length 225764.6075 Horizontal 127522.0800 Vertical 116540.9200
|
||
# Ratio Actual / Manhattan 0.0400
|
||
# Unconnected Length 5450214.5000 Horizontal 1627123.5000 Vertical 3823091.0000
|
||
quit
|