5254 lines
314 KiB
Plaintext
5254 lines
314 KiB
Plaintext
#
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# ===============================================================================
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# Allegro PCB Router
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# Copyright 1990-2010 Cadence Design Systems, Inc. All Rights Reserved.
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# ===============================================================================
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#
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# Software licensed for sale by Cadence Design Systems, Inc.
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# Current time = Mon Mar 09 12:52:58 2015
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#
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# Allegro PCB Router v16-6-112 made 2012/09/12 at 23:00:45
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# Running on: qgpwindowsvb-pc, OS Version: WindowsNT 6.1.7601, Architecture: Intel Pentium II, III, or 4
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# Licensing: The program will not obey any unlicensed rules
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# No graphics will be displayed.
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# Design Name C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
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# Batch File Name: pasde.do
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# Did File Name: C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical/specctra.did
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# Current time = Mon Mar 09 12:52:59 2015
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# PCB C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical
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# Master Unit set up as: MIL 100
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# PCB Limits xlo= 40.0000 ylo=-920.0000 xhi=16760.0000 yhi=16560.0000
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# Total 247 Images Consolidated.
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# Via VIA z=1, 2 xlo=-12.0000 ylo=-12.0000 xhi= 12.0000 yhi= 12.0000
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#
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# VIA TOP BOTTOM
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#
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# TOP ------ VIA
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# BOTTOM VIA ------
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#
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# <<WARNING:>> The * character appears in a net name.
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# * has been disabled as a wildcard character for nets.
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# You can use the wildcard command to change the wildcard character.
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# <<WARNING:>> Net GND is defined as a signal net and contains 436 pins.
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# This is more pins than most signal nets contain.
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# Please verify whether net GND should be a signal net or a power net.
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# Note that a signal net will be routed as starburst or daisy chain.
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# Wires Processed 800, Vias Processed 324
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# Using colormap in design file.
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# Layers Processed: Signal Layers 2
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# Layers Processed: Power Layers 5
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# Components Placed 881, Images Processed 298, Padstacks Processed 23
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# Nets Processed 677, Net Terminals 3037
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# PCB Area=231040000.000 EIC=240 Area/EIC=962666.667 SMDs=611
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# Total Pin Count: 3371
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# Signal Connections Created 1265
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#
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# Design Rules --------------------------------------------
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# Via Grid 0.1000 with offset 0.0000
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# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
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# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
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# Cpu Time = 0:00:00 Elapsed Time = 0:00:00
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#
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# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
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# Nets 677 Connections 2013 Unroutes 1584
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# Signal Layers 2 Power Layers 5
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# Wire Junctions 166, at vias 91 Total Vias 324
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# Percent Connected 14.06
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# Manhattan Length 5098147.5000 Horizontal 1547193.5200 Vertical 3550953.9800
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# Routed Length 222970.2249 Horizontal 133873.9000 Vertical 106105.6000
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# Ratio Actual / Manhattan 0.0437
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# Unconnected Length 4914074.3000 Horizontal 1460183.8000 Vertical 3453890.5000
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# Total Conflicts: 600 (Cross: 13, Clear: 587, Xtalk: 0, Length: 0, Polygon Clear: 0 )
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# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
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# Loading Do File pasde.do ...
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# Loading Do File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC_rules.do ...
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# Nets UNNAMED_1_FRONTPORTS_I2_SYNCP and UNNAMED_1_FRONTPORTS_I2_SYNCN have been defined as a balanced pair.
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# Nets CLK_BAD_P and CLK_BAD_N have been defined as a balanced pair.
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# <<WARNING:>> Could not form pair of nets DEF_CLK_DIV8_P and DEF_CLK_DIV8_N.
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# <<WARNING:>> Could not form pair of nets UNNAMED_1_FRONTPORTS_I2_MTCAM_4 and UNNAMED_1_FRONTPORTS_I2_MTCAM_3.
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# <<WARNING:>> Could not form pair of nets UNNAMED_1_FRONTPORTS_I2_MTCAM_1 and UNNAMED_1_FRONTPORTS_I2_MTCAMIM.
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# <<WARNING:>> Could not form pair of nets UNNAMED_1_FRONTPORTS_I2_RIBBO_3 and UNNAMED_1_FRONTPORTS_I2_RIBBO_2.
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# Nets UNNAMED_1_MC10E116_I4_Q3_1 and UNNAMED_1_MC10E116_I4_Q3 have been defined as a balanced pair.
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# <<WARNING:>> Could not form pair of nets DEF_CLK_DIV4_P and DEF_CLK_DIV4_N.
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# Nets UNNAMED_1_CAENCOMS_I8_GT2P and GT2_N have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I4_Q2_1 and UNNAMED_1_MC10E116_I4_Q2 have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I3_Q3_1 and UNNAMED_1_MC10E116_I3_Q3 have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I4_Q1_1 and UNNAMED_1_MC10E116_I4_Q1 have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I3_Q2_1 and UNNAMED_1_MC10E116_I3_Q2 have been defined as a balanced pair.
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# <<WARNING:>> Could not form pair of nets DEF_CLK_DIV2_P and DEF_CLK_DIV2_N.
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# Nets UNNAMED_1_MC10E116_I4_Q0_1 and UNNAMED_1_MC10E116_I4_Q0 have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I3_Q1_1 and UNNAMED_1_MC10E116_I3_Q1 have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I1_Q3_1 and UNNAMED_1_MC10E116_I1_Q3 have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I3_Q0_1 and UNNAMED_1_MC10E116_I3_Q0 have been defined as a balanced pair.
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# Nets CHOSEN_CLK_P and CHOSEN_CLK_N have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I1_Q0_1 and UNNAMED_1_MC10E116_I1_Q0 have been defined as a balanced pair.
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# Nets UNNAMED_1_CHANGECLKS_I3_CHANG_1 and UNNAMED_1_CHANGECLKS_I3_CHANGEC have been defined as a balanced pair.
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# Nets USE_BCKP_P and USE_BCKP_N have been defined as a balanced pair.
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# Nets TRIG_GATE2_P and TRIG_GATE2_N have been defined as a balanced pair.
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# Nets UNNAMED_1_FRONTPORTS_I2_SYNC24P and UNNAMED_1_FRONTPORTS_I2_SYNC24N have been defined as a balanced pair.
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# Nets TRIG_GATE1_P and TRIG_GATE1_N have been defined as a balanced pair.
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# Nets UNNAMED_1_FRONTPORTS_I2_GTP and UNNAMED_1_FRONTPORTS_I2_GTN have been defined as a balanced pair.
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# Nets BCKP_CLK_BUFD_P and BCKP_CLK_BUFD_N have been defined as a balanced pair.
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# Nets USE_DEFAULT_P and USE_DEFAULT_N have been defined as a balanced pair.
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# Nets SYNC_2_P and SYNC_2_N have been defined as a balanced pair.
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# Nets TELLIE_DELAY_BUF_P and TELLIE_DELAY_BUF_N have been defined as a balanced pair.
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# Nets UNNAMED_1_AD96687_I1_Q2_1 and UNNAMED_1_AD96687_I1_Q2 have been defined as a balanced pair.
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# Nets UNNAMED_1_AD96687_I1_Q1_1 and UNNAMED_1_AD96687_I1_Q1 have been defined as a balanced pair.
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# Nets RIB10_P and RIB10_N have been defined as a balanced pair.
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# Nets UNNAMED_1_DEFAULTCLKSEL_I1_BCKP and UNNAMED_1_MC10E116_I1_D0 have been defined as a balanced pair.
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# <<WARNING:>> Could not form pair of nets UNNAMED_1_FRONTPORTS_I2_SYNCL_1 and UNNAMED_1_FRONTPORTS_I2_SYNCLVD.
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# Nets SYNC24_2_P and SYNC24_2_N have been defined as a balanced pair.
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# <<WARNING:>> Could not form pair of nets UNNAMED_1_FRONTPORTS_I2_CLK100P and UNNAMED_1_FRONTPORTS_I2_CLK100N.
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# Nets UNNAMED_1_MC10E116_I22_Q1_1 and UNNAMED_1_MC10E116_I22_Q1 have been defined as a balanced pair.
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# Nets CHOSEN_CLK2_P and CHOSEN_CLK2_N have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I22_Q0_1 and UNNAMED_1_MC10E116_I22_Q0 have been defined as a balanced pair.
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# Nets UNNAMED_1_CHANGECLKS_I3_BCKPC_3 and UNNAMED_1_CHANGECLKS_I3_BCKPC_2 have been defined as a balanced pair.
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# Nets UNNAMED_1_CHANGECLKS_I3_BCKPC_1 and UNNAMED_1_CHANGECLKS_I3_BCKPCLK have been defined as a balanced pair.
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# <<WARNING:>> Could not form pair of nets UNNAMED_1_FRONTPORTS_I2_SYNC2_1 and UNNAMED_1_FRONTPORTS_I2_SYNC24L.
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# Nets UNNAMED_1_FRONTPORTS_I2_RIBBO_1 and UNNAMED_1_FRONTPORTS_I2_RIBBONP have been defined as a balanced pair.
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# Nets RIB9_P and RIB9_N have been defined as a balanced pair.
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# Nets RIB8_P and RIB8_N have been defined as a balanced pair.
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# Nets RIB7_P and RIB7_N have been defined as a balanced pair.
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# Nets RIB6_P and RIB6_N have been defined as a balanced pair.
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# Nets UNNAMED_1_CSMD0805_I70_B and UNNAMED_1_CSMD0805_I64_B have been defined as a balanced pair.
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# Nets RIB5_P and RIB5_N have been defined as a balanced pair.
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# Nets RIB4_P and RIB4_N have been defined as a balanced pair.
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# Nets RIB3_P and RIB3_N have been defined as a balanced pair.
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# Nets RIB2_P and RIB2_N have been defined as a balanced pair.
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# Nets RIB1_P and RIB1_N have been defined as a balanced pair.
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# <<WARNING:>> Could not form pair of nets UNNAMED_1_FRONTPORTS_I2_EXTT<4> and UNNAMED_1_CSMD0603_I55_A.
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# <<WARNING:>> Could not form pair of nets UNNAMED_1_FRONTPORTS_I2_EXTT<0> and UNNAMED_1_CSMD0603_I54_B.
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# Nets SMELLIE_DELAY_BUF_P and SMELLIE_DELAY_BUF_N have been defined as a balanced pair.
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# Nets CHANGE_CLK2_P and CHANGE_CLK2_N have been defined as a balanced pair.
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# <<WARNING:>> Could not form pair of nets UNNAMED_1_FRONTPORTS_I2_LOSTA_1 and UNNAMED_1_FRONTPORTS_I2_LOSTARO.
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# <<WARNING:>> Could not form pair of nets DEF_CLK_DIVD_P and DEF_CLK_DIVD_N.
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# Nets TRIG_PULS2_P and TRIG_PULS2_N have been defined as a balanced pair.
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# <<WARNING:>> Could not form pair of nets UNNAMED_1_FRONTPORTS_I2_SMELLIE and UNNAMED_1_CSMD0603_I10_B_1.
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# Nets TRIG_PULS1_P and TRIG_PULS1_N have been defined as a balanced pair.
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# Nets UNNAMED_1_FRONTPORTS_I2_ECLTOLV and VBB_TRANS have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I2_D0 and LO_STAR_RAW have been defined as a balanced pair.
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# Nets UNNAMED_1_CHANGECLKS_I3_DEFAU_1 and UNNAMED_1_CHANGECLKS_I3_DEFAULT have been defined as a balanced pair.
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# Colormap Written to File _notify.std
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# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
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# Enter command <# Loading Do File C:/Users/QGPWIN~1/AppData/Local/Temp/#Taaaaas02200.tmp ...
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# All Components Unselected.
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# All Nets Unselected.
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# Component Q2 Selected.
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# Component L1 Selected.
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# Component L2 Selected.
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# Component L4 Selected.
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# Component Q3 Selected.
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# Component Q4 Selected.
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set route_diagonal 4
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grid wire 0.100000 (direction x) (offset 0.000000)
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grid wire 0.100000 (direction y) (offset 0.000000)
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grid via 0.100000 (direction x) (offset 0.000000)
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grid via 0.100000 (direction y) (offset 0.000000)
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protect all wires
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# All Wires Protected.
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direction TOP horizontal
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select layer TOP
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unprotect layer_wires TOP
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# Wires on layer TOP were Unprotected.
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direction BOTTOM vertical
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select layer BOTTOM
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unprotect layer_wires BOTTOM
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# Wires on layer BOTTOM were Unprotected.
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cost via -1
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# System default cost will be used.
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set turbo_stagger off
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limit outside -1
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rule pcb (patterns_allowed trombone accordion)
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set pattern_stacking on
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rule pcb (sawtooth_amplitude -1 -1)
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rule pcb (sawtooth_gap -1)
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rule pcb (accordion_amplitude -1 -1)
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rule pcb (accordion_gap -1)
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rule pcb (trombone_run_length -1)
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rule pcb (trombone_gap -1)
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unprotect selected
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# All Selected Wires Unprotected.
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smart_route (auto_fanout off) (auto_testpoint off) (auto_miter on)
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# Smart Route: Only part of the wires are selected for routing.
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# Using modified smart_route algorithm.
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# Smart Route: Executing 50 route passes.
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# Current time = Mon Mar 09 12:53:21 2015
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#
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# VIA TOP BOTTOM
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#
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# TOP ------ VIA
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# BOTTOM VIA ------
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#
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#
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# Design Rules --------------------------------------------
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# Via Grid 0.1000 with offset 0.0000
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# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
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# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
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#
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# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
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# Nets 677 Connections 2013 Unroutes 1584
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# Signal Layers 2 Power Layers 5
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# Wire Junctions 169, at vias 92 Total Vias 324
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# Percent Connected 20.91
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# Manhattan Length 5113978.2000 Horizontal 1553941.8100 Vertical 3560036.3900
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# Routed Length 222970.2249 Horizontal 133873.9000 Vertical 106105.6000
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# Ratio Actual / Manhattan 0.0436
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# Unconnected Length 4932577.9000 Horizontal 1471714.3000 Vertical 3460863.6000
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# Start Route Pass 1 of 50
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# Routing 12 wires.
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# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
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# Total Unroutes: 1572
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# Attempts 12 Successes 12 Failures 0 Vias 329
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# Cpu Time = 0:00:01 Elapsed Time = 0:00:00
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# End Pass 1 of 50
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# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
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# <<WARNING:>> Smart Route: Unroute count 1584 is very high after 1 passes.
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# Design may not reach 100%.
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# Check placement, components outside boundary, design rules, keepout positions
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# Start Route Pass 2 of 50
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# Routing 0 wires.
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# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
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# Total Unroutes: 1572
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# Attempts 0 Successes 0 Failures 0 Vias 329
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# Cpu Time = 0:00:00 Elapsed Time = 0:00:00
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# End Pass 2 of 50
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# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
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# <<WARNING:>> Smart Route: Conflict reduction rate 0 is very low
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# after 2 passes.
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# Design may not reach 100%.
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# Check number of layers, grids and design rules.
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# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
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#
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# Design Rules --------------------------------------------
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# Via Grid 0.1000 with offset 0.0000
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# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
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# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
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# ROUTING HISTORY ================================================================
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# Pass | Conflicts | | | | | |Red| CPU Time |
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# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
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#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
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# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
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# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
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# Conflicts between polygon wires and fixed objects: 0
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# Stub Violations: 0
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# Net Order Violations: 0
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# Diffpair Uncoupled Length Violations: 0
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# Diffpair Phase Tolerance Violations: 0
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# Total layerset violations: 0
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# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
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# Overall Routing Time: 0:00:01
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#
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# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
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# Nets 677 Connections 2013 Unroutes 1572
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# Signal Layers 2 Power Layers 5
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# Wire Junctions 172, at vias 93 Total Vias 329
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# Percent Connected 21.51
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# Manhattan Length 5113978.2000 Horizontal 1553985.7800 Vertical 3559992.4200
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# Routed Length 233878.6491 Horizontal 140380.9000 Vertical 111991.7000
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# Ratio Actual / Manhattan 0.0457
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# Unconnected Length 4921399.0000 Horizontal 1465925.8000 Vertical 3455473.2000
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# Smart Route: Executing 2 clean passes.
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# Current time = Mon Mar 09 12:53:23 2015
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#
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# VIA TOP BOTTOM
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#
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# TOP ------ VIA
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# BOTTOM VIA ------
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#
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#
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# Design Rules --------------------------------------------
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# Via Grid 0.1000 with offset 0.0000
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# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
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# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
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#
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# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
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# Nets 677 Connections 2013 Unroutes 1572
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# Signal Layers 2 Power Layers 5
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# Wire Junctions 172, at vias 93 Total Vias 329
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# Percent Connected 21.51
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# Manhattan Length 5113978.2000 Horizontal 1553985.7800 Vertical 3559992.4200
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# Routed Length 233878.6491 Horizontal 140380.9000 Vertical 111991.7000
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# Ratio Actual / Manhattan 0.0457
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# Unconnected Length 4921399.0000 Horizontal 1465925.8000 Vertical 3455473.2000
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# Start Clean Pass 1 of 2
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# Routing 17 wires.
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# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
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# Total Unroutes: 1572
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# Attempts 14 Successes 14 Failures 0 Vias 327
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# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
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# End Pass 1 of 2
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# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
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# Start Clean Pass 2 of 2
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# Routing 15 wires.
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# 0 bend points have been removed.
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# 0 bend points have been removed.
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# 0 bend points have been removed.
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# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
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# Total Unroutes: 1572
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# Attempts 15 Successes 15 Failures 0 Vias 327
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# Cpu Time = 0:00:01 Elapsed Time = 0:00:01
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# End Pass 2 of 2
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# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
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# Cpu Time = 0:00:02 Elapsed Time = 0:00:03
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#
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# Design Rules --------------------------------------------
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# Via Grid 0.1000 with offset 0.0000
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# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
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# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
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# ROUTING HISTORY ================================================================
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# Pass | Conflicts | | | | | |Red| CPU Time |
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# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
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#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
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# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
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# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
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# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:02
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 234045.0028 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0457
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 50 route passes.
|
||
# Current time = Mon Mar 09 12:53:27 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 234045.0028 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0457
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Route Pass 1 of 50
|
||
# Routing 0 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 0 Successes 0 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
|
||
# End Pass 1 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# <<WARNING:>> Smart Route: Average reduction ratio only 0 after 3 passes.
|
||
# Design may converge very slowly.
|
||
# Monitor status file carefully.
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:02
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 234045.0028 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0457
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 2 clean passes.
|
||
# Current time = Mon Mar 09 12:53:28 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 234045.0028 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0457
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Clean Pass 1 of 2
|
||
# Routing 15 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
|
||
# End Pass 1 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Start Clean Pass 2 of 2
|
||
# Routing 15 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:01
|
||
# End Pass 2 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:02
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:03
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 234816.6007 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 50 route passes.
|
||
# Current time = Mon Mar 09 12:53:31 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 234816.6007 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Route Pass 1 of 50
|
||
# Routing 0 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 0 Successes 0 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
|
||
# End Pass 1 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# <<WARNING:>> Smart Route: Average reduction ratio only 0 after 4 passes.
|
||
# Design may converge very slowly.
|
||
# Monitor status file carefully.
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:01
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:03
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 234816.6007 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 2 clean passes.
|
||
# Current time = Mon Mar 09 12:53:33 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 234816.6007 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Clean Pass 1 of 2
|
||
# Routing 15 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:00
|
||
# End Pass 1 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Start Clean Pass 2 of 2
|
||
# Routing 15 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:00
|
||
# End Pass 2 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:03
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:04
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 234995.5585 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 50 route passes.
|
||
# Current time = Mon Mar 09 12:53:36 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 234995.5585 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Route Pass 1 of 50
|
||
# Routing 0 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 0 Successes 0 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:00
|
||
# End Pass 1 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# <<WARNING:>> Smart Route: Average reduction ratio only 0 after 5 passes.
|
||
# Design may converge very slowly.
|
||
# Monitor status file carefully.
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:03
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:05
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 234995.5585 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 2 clean passes.
|
||
# Current time = Mon Mar 09 12:53:39 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 234995.5585 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Clean Pass 1 of 2
|
||
# Routing 15 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:01
|
||
# End Pass 1 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Start Clean Pass 2 of 2
|
||
# Routing 15 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:01
|
||
# End Pass 2 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Cpu Time = 0:00:03 Elapsed Time = 0:00:05
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:07
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235040.3126 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 50 route passes.
|
||
# Current time = Mon Mar 09 12:53:44 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235040.3126 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Route Pass 1 of 50
|
||
# Routing 0 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 0 Successes 0 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
|
||
# End Pass 1 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 6 passes.
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:02
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:07
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235040.3126 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 2 clean passes.
|
||
# Current time = Mon Mar 09 12:53:47 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235040.3126 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Clean Pass 1 of 2
|
||
# Routing 15 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:00
|
||
# End Pass 1 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Start Clean Pass 2 of 2
|
||
# Routing 15 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:00
|
||
# End Pass 2 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:03
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:08
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 50 route passes.
|
||
# Current time = Mon Mar 09 12:53:50 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Route Pass 1 of 50
|
||
# Routing 0 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 0 Successes 0 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
|
||
# End Pass 1 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 7 passes.
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:03
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:08
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 2 clean passes.
|
||
# Current time = Mon Mar 09 12:53:53 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Clean Pass 1 of 2
|
||
# Routing 15 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:00
|
||
# End Pass 1 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Start Clean Pass 2 of 2
|
||
# Routing 15 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:00
|
||
# End Pass 2 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:09
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 50 route passes.
|
||
# Current time = Mon Mar 09 12:53:56 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Route Pass 1 of 50
|
||
# Routing 0 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 0 Successes 0 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:00
|
||
# End Pass 1 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 8 passes.
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:02
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:09
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 2 clean passes.
|
||
# Current time = Mon Mar 09 12:53:58 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Clean Pass 1 of 2
|
||
# Routing 15 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
|
||
# End Pass 1 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Start Clean Pass 2 of 2
|
||
# Routing 15 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:01
|
||
# End Pass 2 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:03
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:10
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 50 route passes.
|
||
# Current time = Mon Mar 09 12:54:02 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Route Pass 1 of 50
|
||
# Routing 0 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 0 Successes 0 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
|
||
# End Pass 1 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 9 passes.
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:01
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:10
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 2 clean passes.
|
||
# Current time = Mon Mar 09 12:54:04 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Clean Pass 1 of 2
|
||
# Routing 15 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:00
|
||
# End Pass 1 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Start Clean Pass 2 of 2
|
||
# Routing 15 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:00
|
||
# End Pass 2 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:11
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 50 route passes.
|
||
# Current time = Mon Mar 09 12:54:07 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Route Pass 1 of 50
|
||
# Routing 0 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 0 Successes 0 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:00
|
||
# End Pass 1 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 10 passes.
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:11
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 2 clean passes.
|
||
# Current time = Mon Mar 09 12:54:09 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Clean Pass 1 of 2
|
||
# Routing 15 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
|
||
# End Pass 1 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Start Clean Pass 2 of 2
|
||
# Routing 15 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:01
|
||
# End Pass 2 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:03
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:12
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 50 route passes.
|
||
# Current time = Mon Mar 09 12:54:13 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Route Pass 1 of 50
|
||
# Routing 0 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 0 Successes 0 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
|
||
# End Pass 1 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 11 passes.
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:01
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:12
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 2 clean passes.
|
||
# Current time = Mon Mar 09 12:54:15 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Clean Pass 1 of 2
|
||
# Routing 15 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:00
|
||
# End Pass 1 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Start Clean Pass 2 of 2
|
||
# Routing 15 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:01
|
||
# End Pass 2 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:13
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 50 route passes.
|
||
# Current time = Mon Mar 09 12:54:18 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Route Pass 1 of 50
|
||
# Routing 0 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 0 Successes 0 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:00
|
||
# End Pass 1 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 12 passes.
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:01
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:13
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 2 clean passes.
|
||
# Current time = Mon Mar 09 12:54:20 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Clean Pass 1 of 2
|
||
# Routing 15 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:00
|
||
# End Pass 1 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Start Clean Pass 2 of 2
|
||
# Routing 15 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:00
|
||
# End Pass 2 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:14
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 50 route passes.
|
||
# Current time = Mon Mar 09 12:54:23 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Route Pass 1 of 50
|
||
# Routing 0 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 0 Successes 0 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:00
|
||
# End Pass 1 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 13 passes.
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:02
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:14
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 2 clean passes.
|
||
# Current time = Mon Mar 09 12:54:26 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Clean Pass 1 of 2
|
||
# Routing 15 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:03 Elapsed Time = 0:00:04
|
||
# End Pass 1 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Start Clean Pass 2 of 2
|
||
# Routing 15 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:01
|
||
# End Pass 2 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Cpu Time = 0:00:05 Elapsed Time = 0:00:05
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:18
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 50 route passes.
|
||
# Current time = Mon Mar 09 12:54:32 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Route Pass 1 of 50
|
||
# Routing 0 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 0 Successes 0 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
|
||
# End Pass 1 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 14 passes.
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Route | 38| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:18|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:18
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 2 clean passes.
|
||
# Current time = Mon Mar 09 12:54:35 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Clean Pass 1 of 2
|
||
# Routing 15 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
|
||
# End Pass 1 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Start Clean Pass 2 of 2
|
||
# Routing 15 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:01
|
||
# End Pass 2 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Route | 38| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:18|
|
||
# Clean | 39| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:18|
|
||
# Clean | 40| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:19|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:19
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 50 route passes.
|
||
# Current time = Mon Mar 09 12:54:38 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Route Pass 1 of 50
|
||
# Routing 0 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 0 Successes 0 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:01
|
||
# End Pass 1 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 15 passes.
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Route | 38| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:18|
|
||
# Clean | 39| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:18|
|
||
# Clean | 40| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:19|
|
||
# Route | 41| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:20|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:20
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 2 clean passes.
|
||
# Current time = Mon Mar 09 12:54:41 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Clean Pass 1 of 2
|
||
# Routing 15 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
|
||
# End Pass 1 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Start Clean Pass 2 of 2
|
||
# Routing 15 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:01
|
||
# End Pass 2 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:03
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Route | 38| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:18|
|
||
# Clean | 39| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:18|
|
||
# Clean | 40| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:19|
|
||
# Route | 41| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:20|
|
||
# Clean | 42| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:20|
|
||
# Clean | 43| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:21|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:21
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 50 route passes.
|
||
# Current time = Mon Mar 09 12:54:44 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Route Pass 1 of 50
|
||
# Routing 0 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 0 Successes 0 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:00
|
||
# End Pass 1 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 16 passes.
|
||
# Cpu Time = 0:00:06 Elapsed Time = 0:00:07
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Route | 38| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:18|
|
||
# Clean | 39| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:18|
|
||
# Clean | 40| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:19|
|
||
# Route | 41| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:20|
|
||
# Clean | 42| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:20|
|
||
# Clean | 43| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:21|
|
||
# Route | 44| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:21|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:21
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 2 clean passes.
|
||
# Current time = Mon Mar 09 12:54:52 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Clean Pass 1 of 2
|
||
# Routing 15 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:00
|
||
# End Pass 1 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Start Clean Pass 2 of 2
|
||
# Routing 15 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:00
|
||
# End Pass 2 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:03
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Route | 38| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:18|
|
||
# Clean | 39| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:18|
|
||
# Clean | 40| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:19|
|
||
# Route | 41| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:20|
|
||
# Clean | 42| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:20|
|
||
# Clean | 43| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:21|
|
||
# Route | 44| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:21|
|
||
# Clean | 45| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:22|
|
||
# Clean | 46| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:23|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:23
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 50 route passes.
|
||
# Current time = Mon Mar 09 12:54:55 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Route Pass 1 of 50
|
||
# Routing 0 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 0 Successes 0 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
|
||
# End Pass 1 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 17 passes.
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Route | 38| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:18|
|
||
# Clean | 39| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:18|
|
||
# Clean | 40| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:19|
|
||
# Route | 41| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:20|
|
||
# Clean | 42| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:20|
|
||
# Clean | 43| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:21|
|
||
# Route | 44| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:21|
|
||
# Clean | 45| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:22|
|
||
# Clean | 46| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:23|
|
||
# Route | 47| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:23|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:23
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 2 clean passes.
|
||
# Current time = Mon Mar 09 12:54:58 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Clean Pass 1 of 2
|
||
# Routing 15 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:00
|
||
# End Pass 1 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Start Clean Pass 2 of 2
|
||
# Routing 15 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:00
|
||
# End Pass 2 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Cpu Time = 0:00:06 Elapsed Time = 0:00:08
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Route | 38| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:18|
|
||
# Clean | 39| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:18|
|
||
# Clean | 40| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:19|
|
||
# Route | 41| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:20|
|
||
# Clean | 42| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:20|
|
||
# Clean | 43| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:21|
|
||
# Route | 44| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:21|
|
||
# Clean | 45| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:22|
|
||
# Clean | 46| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:23|
|
||
# Route | 47| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:23|
|
||
# Clean | 48| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:23|
|
||
# Clean | 49| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:24|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:24
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 50 route passes.
|
||
# Current time = Mon Mar 09 12:55:06 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Route Pass 1 of 50
|
||
# Routing 0 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 0 Successes 0 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
|
||
# End Pass 1 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 18 passes.
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:02
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Route | 38| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:18|
|
||
# Clean | 39| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:18|
|
||
# Clean | 40| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:19|
|
||
# Route | 41| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:20|
|
||
# Clean | 42| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:20|
|
||
# Clean | 43| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:21|
|
||
# Route | 44| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:21|
|
||
# Clean | 45| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:22|
|
||
# Clean | 46| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:23|
|
||
# Route | 47| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:23|
|
||
# Clean | 48| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:23|
|
||
# Clean | 49| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:24|
|
||
# Route | 50| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:24|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:24
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 2 clean passes.
|
||
# Current time = Mon Mar 09 12:55:09 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Clean Pass 1 of 2
|
||
# Routing 15 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:00
|
||
# End Pass 1 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Start Clean Pass 2 of 2
|
||
# Routing 15 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
|
||
# End Pass 2 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Route | 38| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:18|
|
||
# Clean | 39| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:18|
|
||
# Clean | 40| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:19|
|
||
# Route | 41| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:20|
|
||
# Clean | 42| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:20|
|
||
# Clean | 43| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:21|
|
||
# Route | 44| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:21|
|
||
# Clean | 45| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:22|
|
||
# Clean | 46| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:23|
|
||
# Route | 47| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:23|
|
||
# Clean | 48| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:23|
|
||
# Clean | 49| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:24|
|
||
# Route | 50| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:24|
|
||
# Clean | 51| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:25|
|
||
# Clean | 52| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:25|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:25
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 50 route passes.
|
||
# Current time = Mon Mar 09 12:55:11 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Route Pass 1 of 50
|
||
# Routing 0 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 0 Successes 0 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
|
||
# End Pass 1 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 19 passes.
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Route | 38| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:18|
|
||
# Clean | 39| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:18|
|
||
# Clean | 40| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:19|
|
||
# Route | 41| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:20|
|
||
# Clean | 42| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:20|
|
||
# Clean | 43| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:21|
|
||
# Route | 44| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:21|
|
||
# Clean | 45| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:22|
|
||
# Clean | 46| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:23|
|
||
# Route | 47| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:23|
|
||
# Clean | 48| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:23|
|
||
# Clean | 49| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:24|
|
||
# Route | 50| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:24|
|
||
# Clean | 51| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:25|
|
||
# Clean | 52| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:25|
|
||
# Route | 53| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:25|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:25
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 2 clean passes.
|
||
# Current time = Mon Mar 09 12:55:13 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Clean Pass 1 of 2
|
||
# Routing 15 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:00
|
||
# End Pass 1 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Start Clean Pass 2 of 2
|
||
# Routing 15 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:00
|
||
# End Pass 2 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:03
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Route | 38| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:18|
|
||
# Clean | 39| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:18|
|
||
# Clean | 40| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:19|
|
||
# Route | 41| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:20|
|
||
# Clean | 42| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:20|
|
||
# Clean | 43| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:21|
|
||
# Route | 44| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:21|
|
||
# Clean | 45| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:22|
|
||
# Clean | 46| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:23|
|
||
# Route | 47| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:23|
|
||
# Clean | 48| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:23|
|
||
# Clean | 49| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:24|
|
||
# Route | 50| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:24|
|
||
# Clean | 51| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:25|
|
||
# Clean | 52| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:25|
|
||
# Route | 53| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:25|
|
||
# Clean | 54| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:26|
|
||
# Clean | 55| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:27|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:27
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 50 route passes.
|
||
# Current time = Mon Mar 09 12:55:16 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Route Pass 1 of 50
|
||
# Routing 0 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 0 Successes 0 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:01
|
||
# End Pass 1 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 20 passes.
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:03
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Route | 38| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:18|
|
||
# Clean | 39| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:18|
|
||
# Clean | 40| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:19|
|
||
# Route | 41| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:20|
|
||
# Clean | 42| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:20|
|
||
# Clean | 43| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:21|
|
||
# Route | 44| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:21|
|
||
# Clean | 45| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:22|
|
||
# Clean | 46| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:23|
|
||
# Route | 47| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:23|
|
||
# Clean | 48| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:23|
|
||
# Clean | 49| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:24|
|
||
# Route | 50| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:24|
|
||
# Clean | 51| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:25|
|
||
# Clean | 52| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:25|
|
||
# Route | 53| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:25|
|
||
# Clean | 54| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:26|
|
||
# Clean | 55| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:27|
|
||
# Route | 56| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:28|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:28
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 2 clean passes.
|
||
# Current time = Mon Mar 09 12:55:19 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Clean Pass 1 of 2
|
||
# Routing 15 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:01
|
||
# End Pass 1 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Start Clean Pass 2 of 2
|
||
# Routing 15 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
|
||
# End Pass 2 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:03
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Route | 38| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:18|
|
||
# Clean | 39| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:18|
|
||
# Clean | 40| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:19|
|
||
# Route | 41| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:20|
|
||
# Clean | 42| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:20|
|
||
# Clean | 43| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:21|
|
||
# Route | 44| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:21|
|
||
# Clean | 45| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:22|
|
||
# Clean | 46| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:23|
|
||
# Route | 47| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:23|
|
||
# Clean | 48| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:23|
|
||
# Clean | 49| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:24|
|
||
# Route | 50| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:24|
|
||
# Clean | 51| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:25|
|
||
# Clean | 52| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:25|
|
||
# Route | 53| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:25|
|
||
# Clean | 54| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:26|
|
||
# Clean | 55| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:27|
|
||
# Route | 56| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:28|
|
||
# Clean | 57| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:29|
|
||
# Clean | 58| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:29|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:29
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 50 route passes.
|
||
# Current time = Mon Mar 09 12:55:23 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Route Pass 1 of 50
|
||
# Routing 0 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 0 Successes 0 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
|
||
# End Pass 1 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 21 passes.
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:02
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Route | 38| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:18|
|
||
# Clean | 39| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:18|
|
||
# Clean | 40| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:19|
|
||
# Route | 41| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:20|
|
||
# Clean | 42| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:20|
|
||
# Clean | 43| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:21|
|
||
# Route | 44| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:21|
|
||
# Clean | 45| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:22|
|
||
# Clean | 46| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:23|
|
||
# Route | 47| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:23|
|
||
# Clean | 48| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:23|
|
||
# Clean | 49| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:24|
|
||
# Route | 50| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:24|
|
||
# Clean | 51| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:25|
|
||
# Clean | 52| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:25|
|
||
# Route | 53| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:25|
|
||
# Clean | 54| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:26|
|
||
# Clean | 55| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:27|
|
||
# Route | 56| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:28|
|
||
# Clean | 57| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:29|
|
||
# Clean | 58| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:29|
|
||
# Route | 59| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:29|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:29
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 2 clean passes.
|
||
# Current time = Mon Mar 09 12:55:25 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Clean Pass 1 of 2
|
||
# Routing 15 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
|
||
# End Pass 1 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Start Clean Pass 2 of 2
|
||
# Routing 15 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:01
|
||
# End Pass 2 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:04
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Route | 38| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:18|
|
||
# Clean | 39| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:18|
|
||
# Clean | 40| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:19|
|
||
# Route | 41| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:20|
|
||
# Clean | 42| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:20|
|
||
# Clean | 43| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:21|
|
||
# Route | 44| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:21|
|
||
# Clean | 45| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:22|
|
||
# Clean | 46| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:23|
|
||
# Route | 47| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:23|
|
||
# Clean | 48| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:23|
|
||
# Clean | 49| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:24|
|
||
# Route | 50| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:24|
|
||
# Clean | 51| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:25|
|
||
# Clean | 52| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:25|
|
||
# Route | 53| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:25|
|
||
# Clean | 54| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:26|
|
||
# Clean | 55| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:27|
|
||
# Route | 56| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:28|
|
||
# Clean | 57| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:29|
|
||
# Clean | 58| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:29|
|
||
# Route | 59| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:29|
|
||
# Clean | 60| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:29|
|
||
# Clean | 61| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:30|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:30
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 50 route passes.
|
||
# Current time = Mon Mar 09 12:55:29 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Route Pass 1 of 50
|
||
# Routing 0 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 0 Successes 0 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
|
||
# End Pass 1 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 22 passes.
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Route | 38| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:18|
|
||
# Clean | 39| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:18|
|
||
# Clean | 40| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:19|
|
||
# Route | 41| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:20|
|
||
# Clean | 42| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:20|
|
||
# Clean | 43| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:21|
|
||
# Route | 44| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:21|
|
||
# Clean | 45| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:22|
|
||
# Clean | 46| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:23|
|
||
# Route | 47| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:23|
|
||
# Clean | 48| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:23|
|
||
# Clean | 49| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:24|
|
||
# Route | 50| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:24|
|
||
# Clean | 51| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:25|
|
||
# Clean | 52| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:25|
|
||
# Route | 53| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:25|
|
||
# Clean | 54| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:26|
|
||
# Clean | 55| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:27|
|
||
# Route | 56| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:28|
|
||
# Clean | 57| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:29|
|
||
# Clean | 58| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:29|
|
||
# Route | 59| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:29|
|
||
# Clean | 60| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:29|
|
||
# Clean | 61| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:30|
|
||
# Route | 62| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:30|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:30
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 2 clean passes.
|
||
# Current time = Mon Mar 09 12:55:32 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Clean Pass 1 of 2
|
||
# Routing 15 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:05 Elapsed Time = 0:00:06
|
||
# End Pass 1 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Start Clean Pass 2 of 2
|
||
# Routing 15 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:00
|
||
# End Pass 2 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Cpu Time = 0:00:11 Elapsed Time = 0:00:13
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Route | 38| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:18|
|
||
# Clean | 39| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:18|
|
||
# Clean | 40| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:19|
|
||
# Route | 41| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:20|
|
||
# Clean | 42| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:20|
|
||
# Clean | 43| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:21|
|
||
# Route | 44| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:21|
|
||
# Clean | 45| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:22|
|
||
# Clean | 46| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:23|
|
||
# Route | 47| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:23|
|
||
# Clean | 48| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:23|
|
||
# Clean | 49| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:24|
|
||
# Route | 50| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:24|
|
||
# Clean | 51| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:25|
|
||
# Clean | 52| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:25|
|
||
# Route | 53| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:25|
|
||
# Clean | 54| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:26|
|
||
# Clean | 55| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:27|
|
||
# Route | 56| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:28|
|
||
# Clean | 57| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:29|
|
||
# Clean | 58| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:29|
|
||
# Route | 59| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:29|
|
||
# Clean | 60| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:29|
|
||
# Clean | 61| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:30|
|
||
# Route | 62| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:30|
|
||
# Clean | 63| 3| 7| 0| 1572| 326| 0| 0| | 0:00:05| 0:00:35|
|
||
# Clean | 64| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:35|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:35
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 50 route passes.
|
||
# Current time = Mon Mar 09 12:55:45 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Route Pass 1 of 50
|
||
# Routing 0 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 0 Successes 0 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
|
||
# End Pass 1 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 23 passes.
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Route | 38| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:18|
|
||
# Clean | 39| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:18|
|
||
# Clean | 40| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:19|
|
||
# Route | 41| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:20|
|
||
# Clean | 42| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:20|
|
||
# Clean | 43| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:21|
|
||
# Route | 44| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:21|
|
||
# Clean | 45| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:22|
|
||
# Clean | 46| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:23|
|
||
# Route | 47| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:23|
|
||
# Clean | 48| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:23|
|
||
# Clean | 49| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:24|
|
||
# Route | 50| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:24|
|
||
# Clean | 51| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:25|
|
||
# Clean | 52| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:25|
|
||
# Route | 53| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:25|
|
||
# Clean | 54| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:26|
|
||
# Clean | 55| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:27|
|
||
# Route | 56| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:28|
|
||
# Clean | 57| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:29|
|
||
# Clean | 58| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:29|
|
||
# Route | 59| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:29|
|
||
# Clean | 60| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:29|
|
||
# Clean | 61| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:30|
|
||
# Route | 62| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:30|
|
||
# Clean | 63| 3| 7| 0| 1572| 326| 0| 0| | 0:00:05| 0:00:35|
|
||
# Clean | 64| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:35|
|
||
# Route | 65| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:35|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:35
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 2 clean passes.
|
||
# Current time = Mon Mar 09 12:55:48 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Clean Pass 1 of 2
|
||
# Routing 15 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:00
|
||
# End Pass 1 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Start Clean Pass 2 of 2
|
||
# Routing 15 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:00
|
||
# End Pass 2 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:03
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Route | 38| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:18|
|
||
# Clean | 39| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:18|
|
||
# Clean | 40| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:19|
|
||
# Route | 41| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:20|
|
||
# Clean | 42| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:20|
|
||
# Clean | 43| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:21|
|
||
# Route | 44| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:21|
|
||
# Clean | 45| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:22|
|
||
# Clean | 46| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:23|
|
||
# Route | 47| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:23|
|
||
# Clean | 48| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:23|
|
||
# Clean | 49| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:24|
|
||
# Route | 50| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:24|
|
||
# Clean | 51| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:25|
|
||
# Clean | 52| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:25|
|
||
# Route | 53| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:25|
|
||
# Clean | 54| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:26|
|
||
# Clean | 55| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:27|
|
||
# Route | 56| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:28|
|
||
# Clean | 57| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:29|
|
||
# Clean | 58| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:29|
|
||
# Route | 59| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:29|
|
||
# Clean | 60| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:29|
|
||
# Clean | 61| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:30|
|
||
# Route | 62| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:30|
|
||
# Clean | 63| 3| 7| 0| 1572| 326| 0| 0| | 0:00:05| 0:00:35|
|
||
# Clean | 64| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:35|
|
||
# Route | 65| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:35|
|
||
# Clean | 66| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:35|
|
||
# Clean | 67| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:36|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:36
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 50 route passes.
|
||
# Current time = Mon Mar 09 12:55:51 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Route Pass 1 of 50
|
||
# Routing 0 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 0 Successes 0 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:01
|
||
# End Pass 1 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 24 passes.
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:02
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Route | 38| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:18|
|
||
# Clean | 39| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:18|
|
||
# Clean | 40| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:19|
|
||
# Route | 41| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:20|
|
||
# Clean | 42| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:20|
|
||
# Clean | 43| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:21|
|
||
# Route | 44| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:21|
|
||
# Clean | 45| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:22|
|
||
# Clean | 46| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:23|
|
||
# Route | 47| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:23|
|
||
# Clean | 48| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:23|
|
||
# Clean | 49| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:24|
|
||
# Route | 50| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:24|
|
||
# Clean | 51| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:25|
|
||
# Clean | 52| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:25|
|
||
# Route | 53| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:25|
|
||
# Clean | 54| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:26|
|
||
# Clean | 55| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:27|
|
||
# Route | 56| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:28|
|
||
# Clean | 57| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:29|
|
||
# Clean | 58| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:29|
|
||
# Route | 59| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:29|
|
||
# Clean | 60| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:29|
|
||
# Clean | 61| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:30|
|
||
# Route | 62| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:30|
|
||
# Clean | 63| 3| 7| 0| 1572| 326| 0| 0| | 0:00:05| 0:00:35|
|
||
# Clean | 64| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:35|
|
||
# Route | 65| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:35|
|
||
# Clean | 66| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:35|
|
||
# Clean | 67| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:36|
|
||
# Route | 68| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:37|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:37
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 2 clean passes.
|
||
# Current time = Mon Mar 09 12:55:53 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Clean Pass 1 of 2
|
||
# Routing 15 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
|
||
# End Pass 1 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Start Clean Pass 2 of 2
|
||
# Routing 15 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:01
|
||
# End Pass 2 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:03
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Route | 38| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:18|
|
||
# Clean | 39| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:18|
|
||
# Clean | 40| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:19|
|
||
# Route | 41| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:20|
|
||
# Clean | 42| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:20|
|
||
# Clean | 43| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:21|
|
||
# Route | 44| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:21|
|
||
# Clean | 45| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:22|
|
||
# Clean | 46| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:23|
|
||
# Route | 47| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:23|
|
||
# Clean | 48| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:23|
|
||
# Clean | 49| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:24|
|
||
# Route | 50| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:24|
|
||
# Clean | 51| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:25|
|
||
# Clean | 52| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:25|
|
||
# Route | 53| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:25|
|
||
# Clean | 54| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:26|
|
||
# Clean | 55| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:27|
|
||
# Route | 56| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:28|
|
||
# Clean | 57| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:29|
|
||
# Clean | 58| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:29|
|
||
# Route | 59| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:29|
|
||
# Clean | 60| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:29|
|
||
# Clean | 61| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:30|
|
||
# Route | 62| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:30|
|
||
# Clean | 63| 3| 7| 0| 1572| 326| 0| 0| | 0:00:05| 0:00:35|
|
||
# Clean | 64| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:35|
|
||
# Route | 65| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:35|
|
||
# Clean | 66| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:35|
|
||
# Clean | 67| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:36|
|
||
# Route | 68| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:37|
|
||
# Clean | 69| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:37|
|
||
# Clean | 70| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:38|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:38
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 50 route passes.
|
||
# Current time = Mon Mar 09 12:55:57 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Route Pass 1 of 50
|
||
# Routing 0 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 0 Successes 0 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:00
|
||
# End Pass 1 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Smart Route: Smart_route progressing normally after 25 passes.
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:02
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Route | 38| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:18|
|
||
# Clean | 39| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:18|
|
||
# Clean | 40| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:19|
|
||
# Route | 41| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:20|
|
||
# Clean | 42| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:20|
|
||
# Clean | 43| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:21|
|
||
# Route | 44| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:21|
|
||
# Clean | 45| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:22|
|
||
# Clean | 46| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:23|
|
||
# Route | 47| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:23|
|
||
# Clean | 48| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:23|
|
||
# Clean | 49| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:24|
|
||
# Route | 50| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:24|
|
||
# Clean | 51| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:25|
|
||
# Clean | 52| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:25|
|
||
# Route | 53| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:25|
|
||
# Clean | 54| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:26|
|
||
# Clean | 55| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:27|
|
||
# Route | 56| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:28|
|
||
# Clean | 57| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:29|
|
||
# Clean | 58| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:29|
|
||
# Route | 59| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:29|
|
||
# Clean | 60| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:29|
|
||
# Clean | 61| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:30|
|
||
# Route | 62| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:30|
|
||
# Clean | 63| 3| 7| 0| 1572| 326| 0| 0| | 0:00:05| 0:00:35|
|
||
# Clean | 64| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:35|
|
||
# Route | 65| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:35|
|
||
# Clean | 66| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:35|
|
||
# Clean | 67| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:36|
|
||
# Route | 68| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:37|
|
||
# Clean | 69| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:37|
|
||
# Clean | 70| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:38|
|
||
# Route | 71| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:39|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:39
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 2 clean passes.
|
||
# Current time = Mon Mar 09 12:55:59 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Clean Pass 1 of 2
|
||
# Routing 15 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:00
|
||
# End Pass 1 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Start Clean Pass 2 of 2
|
||
# Routing 15 wires.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# 0 bend points have been removed.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 15 Successes 15 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:00 Elapsed Time = 0:00:01
|
||
# End Pass 2 of 2
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# Cpu Time = 0:00:02 Elapsed Time = 0:00:03
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Route | 38| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:18|
|
||
# Clean | 39| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:18|
|
||
# Clean | 40| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:19|
|
||
# Route | 41| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:20|
|
||
# Clean | 42| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:20|
|
||
# Clean | 43| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:21|
|
||
# Route | 44| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:21|
|
||
# Clean | 45| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:22|
|
||
# Clean | 46| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:23|
|
||
# Route | 47| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:23|
|
||
# Clean | 48| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:23|
|
||
# Clean | 49| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:24|
|
||
# Route | 50| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:24|
|
||
# Clean | 51| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:25|
|
||
# Clean | 52| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:25|
|
||
# Route | 53| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:25|
|
||
# Clean | 54| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:26|
|
||
# Clean | 55| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:27|
|
||
# Route | 56| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:28|
|
||
# Clean | 57| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:29|
|
||
# Clean | 58| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:29|
|
||
# Route | 59| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:29|
|
||
# Clean | 60| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:29|
|
||
# Clean | 61| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:30|
|
||
# Route | 62| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:30|
|
||
# Clean | 63| 3| 7| 0| 1572| 326| 0| 0| | 0:00:05| 0:00:35|
|
||
# Clean | 64| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:35|
|
||
# Route | 65| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:35|
|
||
# Clean | 66| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:35|
|
||
# Clean | 67| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:36|
|
||
# Route | 68| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:37|
|
||
# Clean | 69| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:37|
|
||
# Clean | 70| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:38|
|
||
# Route | 71| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:39|
|
||
# Clean | 72| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:39|
|
||
# Clean | 73| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:39|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:39
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Smart Route: Executing 50 route passes.
|
||
# Current time = Mon Mar 09 12:56:03 2015
|
||
#
|
||
# VIA TOP BOTTOM
|
||
#
|
||
# TOP ------ VIA
|
||
# BOTTOM VIA ------
|
||
#
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# Start Route Pass 1 of 50
|
||
# Routing 0 wires.
|
||
# Total Conflicts: 10 (Cross: 3, Clear: 7, Xtalk: 0, Length: 0, Polygon Clear: 0 )
|
||
# Total Unroutes: 1572
|
||
# Attempts 0 Successes 0 Failures 0 Vias 326
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:00
|
||
# End Pass 1 of 50
|
||
# Wiring Written to File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\bestsave.w
|
||
# <<ERROR:>> Smart Route: Design is unroutable, not enough resources.
|
||
# Many unroutes will exist if you use the filter command.
|
||
# Check number of layers, grids, design rules and placement.
|
||
# Cpu Time = 0:00:01 Elapsed Time = 0:00:02
|
||
#
|
||
# Design Rules --------------------------------------------
|
||
# Via Grid 0.1000 with offset 0.0000
|
||
# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
|
||
# ROUTING HISTORY ================================================================
|
||
# Pass | Conflicts | | | | | |Red| CPU Time |
|
||
# Name |No.| Cross| Clear|Fail|Unrte| Vias|XTalk|Len.| % | Pass | Total |
|
||
#----------+---+------+------+----+-----+-----+-----+----+---+---------+---------|
|
||
# Route | 1| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:01| 0:00:01|
|
||
# Route | 2| 3| 7| 0| 1572| 329| 0| 0| 0| 0:00:00| 0:00:01|
|
||
# Clean | 3| 3| 7| 0| 1572| 327| 0| 0| | 0:00:00| 0:00:01|
|
||
# Clean | 4| 3| 7| 0| 1572| 327| 0| 0| | 0:00:01| 0:00:02|
|
||
# Route | 5| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:02|
|
||
# Clean | 6| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:02|
|
||
# Clean | 7| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:03|
|
||
# Route | 8| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:03|
|
||
# Clean | 9| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:03|
|
||
# Clean | 10| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:04|
|
||
# Route | 11| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:05|
|
||
# Clean | 12| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:06|
|
||
# Clean | 13| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:07|
|
||
# Route | 14| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:07|
|
||
# Clean | 15| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:08|
|
||
# Clean | 16| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Route | 17| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:08|
|
||
# Clean | 18| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:08|
|
||
# Clean | 19| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:09|
|
||
# Route | 20| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:09|
|
||
# Clean | 21| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:09|
|
||
# Clean | 22| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:10|
|
||
# Route | 23| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:10|
|
||
# Clean | 24| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:10|
|
||
# Clean | 25| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:11|
|
||
# Route | 26| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:11|
|
||
# Clean | 27| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:11|
|
||
# Clean | 28| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:12|
|
||
# Route | 29| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:12|
|
||
# Clean | 30| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:12|
|
||
# Clean | 31| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:13|
|
||
# Route | 32| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:13|
|
||
# Clean | 33| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:13|
|
||
# Clean | 34| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:14|
|
||
# Route | 35| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:14|
|
||
# Clean | 36| 3| 7| 0| 1572| 326| 0| 0| | 0:00:03| 0:00:17|
|
||
# Clean | 37| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:18|
|
||
# Route | 38| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:18|
|
||
# Clean | 39| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:18|
|
||
# Clean | 40| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:19|
|
||
# Route | 41| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:20|
|
||
# Clean | 42| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:20|
|
||
# Clean | 43| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:21|
|
||
# Route | 44| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:21|
|
||
# Clean | 45| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:22|
|
||
# Clean | 46| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:23|
|
||
# Route | 47| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:23|
|
||
# Clean | 48| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:23|
|
||
# Clean | 49| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:24|
|
||
# Route | 50| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:24|
|
||
# Clean | 51| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:25|
|
||
# Clean | 52| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:25|
|
||
# Route | 53| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:25|
|
||
# Clean | 54| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:26|
|
||
# Clean | 55| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:27|
|
||
# Route | 56| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:28|
|
||
# Clean | 57| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:29|
|
||
# Clean | 58| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:29|
|
||
# Route | 59| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:29|
|
||
# Clean | 60| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:29|
|
||
# Clean | 61| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:30|
|
||
# Route | 62| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:30|
|
||
# Clean | 63| 3| 7| 0| 1572| 326| 0| 0| | 0:00:05| 0:00:35|
|
||
# Clean | 64| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:35|
|
||
# Route | 65| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:00| 0:00:35|
|
||
# Clean | 66| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:35|
|
||
# Clean | 67| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:36|
|
||
# Route | 68| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:37|
|
||
# Clean | 69| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:37|
|
||
# Clean | 70| 3| 7| 0| 1572| 326| 0| 0| | 0:00:01| 0:00:38|
|
||
# Route | 71| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:39|
|
||
# Clean | 72| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:39|
|
||
# Clean | 73| 3| 7| 0| 1572| 326| 0| 0| | 0:00:00| 0:00:39|
|
||
# Route | 74| 3| 7| 0| 1572| 326| 0| 0| 0| 0:00:01| 0:00:40|
|
||
# Conflicts between polygon wires and fixed objects: 0
|
||
# Stub Violations: 0
|
||
# Net Order Violations: 0
|
||
# Diffpair Uncoupled Length Violations: 0
|
||
# Diffpair Phase Tolerance Violations: 0
|
||
# Total layerset violations: 0
|
||
# Total layerset violations (exclude Fanout/Stagger/XNet Short side): 0
|
||
# Overall Routing Time: 0:00:40
|
||
#
|
||
# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
|
||
# Nets 677 Connections 2013 Unroutes 1572
|
||
# Signal Layers 2 Power Layers 5
|
||
# Wire Junctions 173, at vias 94 Total Vias 326
|
||
# Percent Connected 21.51
|
||
# Manhattan Length 5116105.9000 Horizontal 1555541.6500 Vertical 3560564.2500
|
||
# Routed Length 235055.2501 Horizontal 140311.9000 Vertical 112023.2000
|
||
# Ratio Actual / Manhattan 0.0459
|
||
# Unconnected Length 4922483.6000 Horizontal 1466425.8000 Vertical 3456057.8000
|
||
# <<ERROR:>> Smart Route: Smart_route command aborting due to failures.
|
||
write routes (changed_only) (reset_changed) C:/Users/QGPWIN~1/AppData/Local/Temp/#Taaaaat02200.tmp
|
||
# Routing Written to File C:/Users/QGPWIN~1/AppData/Local/Temp/#Taaaaat02200.tmp
|
||
quit
|