141 lines
9.8 KiB
Plaintext
141 lines
9.8 KiB
Plaintext
#
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# ===============================================================================
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# Allegro PCB Router
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# Copyright 1990-2010 Cadence Design Systems, Inc. All Rights Reserved.
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# ===============================================================================
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#
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# Software licensed for sale by Cadence Design Systems, Inc.
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# Current time = Thu Apr 23 11:27:31 2015
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#
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# Allegro PCB Router v16-6-112 made 2012/09/12 at 23:00:45
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# Running on: qgpwindowsvb-pc, OS Version: WindowsNT 6.1.7601, Architecture: Intel Pentium II, III, or 4
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# Licensing: The program will not obey any unlicensed rules
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# No graphics will be displayed.
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# Design Name C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\TubiiPCB_V3.dsn
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# Batch File Name: pasde.do
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# Did File Name: C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical/specctra.did
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# Current time = Thu Apr 23 11:27:32 2015
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# PCB C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical
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# Master Unit set up as: MIL 100
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# PCB Limits xlo= 40.0000 ylo=-920.0000 xhi=16760.0000 yhi=16560.0000
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# Total 838 Images Consolidated.
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# Via VIA z=1, 2 xlo=-12.0000 ylo=-12.0000 xhi= 12.0000 yhi= 12.0000
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#
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# VIA TOP BOTTOM
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#
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# TOP ------ VIA
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# BOTTOM VIA ------
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#
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# <<WARNING:>> The * character appears in a net name.
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# * has been disabled as a wildcard character for nets.
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# You can use the wildcard command to change the wildcard character.
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# <<WARNING:>> Net GND is defined as a signal net and contains 517 pins.
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# This is more pins than most signal nets contain.
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# Please verify whether net GND should be a signal net or a power net.
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# Note that a signal net will be routed as starburst or daisy chain.
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# Wires Processed 2748, Vias Processed 1039
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# Using colormap in design file.
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# Layers Processed: Signal Layers 2
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# Layers Processed: Power Layers 5
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# Components Placed 872, Images Processed 909, Padstacks Processed 26
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# Nets Processed 640, Net Terminals 3835
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# PCB Area=231040000.000 EIC=244 Area/EIC=946885.246 SMDs=645
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# Total Pin Count: 3419
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# Signal Connections Created 372
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#
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# Design Rules --------------------------------------------
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# Via Grid 0.1000 with offset 0.0000
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# Layer TOP Horz Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
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# Layer BOTTOM Vert Signal Wire Grid 0.1000 with offset 0.0000, Width= 7.0000, Clearance= 7.0000
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# Cpu Time = 0:00:00 Elapsed Time = 0:00:00
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#
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# Wiring Statistics ----------------- C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\TubiiPCB_V3.dsn
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# Nets 640 Connections 2132 Unroutes 447
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# Signal Layers 2 Power Layers 5
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# Wire Junctions 463, at vias 211 Total Vias 1036
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# Percent Connected 71.67
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# Manhattan Length 1513535.8000 Horizontal 642622.2300 Vertical 870913.5700
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# Routed Length 1396764.5628 Horizontal 665592.1000 Vertical 898243.9000
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# Ratio Actual / Manhattan 0.9228
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# Unconnected Length 197915.3000 Horizontal 90702.4000 Vertical 107212.9000
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# Total Conflicts: 1311 (Cross: 2, Clear: 1309, Xtalk: 0, Length: 0, Polygon Clear: 0 )
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# Cpu Time = 0:00:01 Elapsed Time = 0:00:01
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# Loading Do File pasde.do ...
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# Loading Do File C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\TubiiPCB_V3_rules.do ...
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# Nets UNNAMED_1_FRONTPORTS_I2_SYNCP and UNNAMED_1_FRONTPORTS_I2_SYNCN have been defined as a balanced pair.
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# Nets CLK_BAD_P and CLK_BAD_N have been defined as a balanced pair.
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# Nets DEF_CLK_DIV8_P and DEF_CLK_DIV8_N have been defined as a balanced pair.
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# Nets UNNAMED_1_FRONTPORTS_I2_MTCAM_4 and UNNAMED_1_FRONTPORTS_I2_MTCAM_3 have been defined as a balanced pair.
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# Nets UNNAMED_1_FRONTPORTS_I2_MTCAM_1 and UNNAMED_1_FRONTPORTS_I2_MTCAMIM have been defined as a balanced pair.
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# Nets UNNAMED_1_FRONTPORTS_I2_RIBBO_3 and UNNAMED_1_FRONTPORTS_I2_RIBBO_2 have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I4_Q3_1 and UNNAMED_1_MC10E116_I4_Q3 have been defined as a balanced pair.
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# Nets DEF_CLK_DIV4_P and DEF_CLK_DIV4_N have been defined as a balanced pair.
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# Nets UNNAMED_1_CAENCOMS_I8_GT2P and GT2_N have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I4_Q2_1 and UNNAMED_1_MC10E116_I4_Q2 have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I3_Q3_1 and UNNAMED_1_MC10E116_I3_Q3 have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I4_Q1_1 and UNNAMED_1_MC10E116_I4_Q1 have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I3_Q2_1 and UNNAMED_1_MC10E116_I3_Q2 have been defined as a balanced pair.
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# Nets DEF_CLK_DIV2_P and DEF_CLK_DIV2_N have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I4_Q0_1 and UNNAMED_1_MC10E116_I4_Q0 have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I3_Q1_1 and UNNAMED_1_MC10E116_I3_Q1 have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I1_Q3_1 and UNNAMED_1_MC10E116_I1_Q3 have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I3_Q0_1 and UNNAMED_1_MC10E116_I3_Q0 have been defined as a balanced pair.
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# Nets CHOSEN_CLK_P and CHOSEN_CLK_N have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I1_Q0_1 and UNNAMED_1_MC10E116_I1_Q0 have been defined as a balanced pair.
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# Nets UNNAMED_1_CHANGECLKS_I3_CHANG_1 and UNNAMED_1_CHANGECLKS_I3_CHANGEC have been defined as a balanced pair.
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# Nets ECAL_ACTIVE_ECL_P and ECAL_ACTIVE_ECL_N have been defined as a balanced pair.
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# Nets USE_BCKP_P and USE_BCKP_N have been defined as a balanced pair.
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# Nets TRIG_GATE2_P and TRIG_GATE2_N have been defined as a balanced pair.
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# Nets UNNAMED_1_FRONTPORTS_I2_SYNC24P and UNNAMED_1_FRONTPORTS_I2_SYNC24N have been defined as a balanced pair.
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# Nets TRIG_GATE1_P and TRIG_GATE1_N have been defined as a balanced pair.
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# Nets UNNAMED_1_FRONTPORTS_I2_GTP and UNNAMED_1_FRONTPORTS_I2_GTN have been defined as a balanced pair.
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# Nets BCKP_CLK_BUFD_P and BCKP_CLK_BUFD_N have been defined as a balanced pair.
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# Nets USE_DEFAULT_P and USE_DEFAULT_N have been defined as a balanced pair.
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# Nets SYNC_2_P and SYNC_2_N have been defined as a balanced pair.
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# Nets CLK_SEL_ECL_P and CLK_SEL_ECL_N have been defined as a balanced pair.
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# <<WARNING:>> Could not form pair of nets FUZZD_CLK_P and FUZZD_CLK_N.
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# Nets FOX_CLK_LVPECL_P and FOX_CLK_LVPECL_N have been defined as a balanced pair.
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# Nets TELLIE_DELAY_BUF_P and TELLIE_DELAY_BUF_N have been defined as a balanced pair.
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# Nets UNNAMED_1_AD96687_I1_Q2_1 and UNNAMED_1_AD96687_I1_Q2 have been defined as a balanced pair.
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# Nets UNNAMED_1_AD96687_I1_Q1_1 and UNNAMED_1_AD96687_I1_Q1 have been defined as a balanced pair.
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# Nets RIB10_P and RIB10_N have been defined as a balanced pair.
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# Nets UNNAMED_1_DEFAULTCLKSEL_I1_BCKP and UNNAMED_1_MC10E116_I1_D0 have been defined as a balanced pair.
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# Nets UNNAMED_1_FRONTPORTS_I2_SYNCL_1 and UNNAMED_1_FRONTPORTS_I2_SYNCLVD have been defined as a balanced pair.
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# Nets SYNC24_2_P and SYNC24_2_N have been defined as a balanced pair.
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# Nets UNNAMED_1_FRONTPORTS_I2_DGTP and UNNAMED_1_FRONTPORTS_I2_DGTN have been defined as a balanced pair.
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# Nets UNNAMED_1_FRONTPORTS_I2_LVDST_1 and UNNAMED_1_FRONTPORTS_I2_LVDSTOE have been defined as a balanced pair.
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# Nets UNNAMED_1_FRONTPORTS_I2_ECLTO_2 and UNNAMED_1_FRONTPORTS_I2_ECLTO_1 have been defined as a balanced pair.
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# Nets UNNAMED_1_FRONTPORTS_I2_CLK100P and UNNAMED_1_FRONTPORTS_I2_CLK100N have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I22_Q1_1 and UNNAMED_1_MC10E116_I22_Q1 have been defined as a balanced pair.
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# Nets CHOSEN_CLK2_P and CHOSEN_CLK2_N have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I22_Q0_1 and UNNAMED_1_MC10E116_I22_Q0 have been defined as a balanced pair.
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# Nets UNNAMED_1_CHANGECLKS_I3_BCKPC_3 and UNNAMED_1_CHANGECLKS_I3_BCKPC_2 have been defined as a balanced pair.
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# Nets UNNAMED_1_CHANGECLKS_I3_BCKPC_1 and UNNAMED_1_CHANGECLKS_I3_BCKPCLK have been defined as a balanced pair.
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# Nets LO_SEL_ECL_P and LO_SEL_ECL_N have been defined as a balanced pair.
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# Nets UNNAMED_1_FRONTPORTS_I2_SYNC2_1 and UNNAMED_1_FRONTPORTS_I2_SYNC24L have been defined as a balanced pair.
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# Nets UNNAMED_1_FRONTPORTS_I2_RIBBO_1 and UNNAMED_1_FRONTPORTS_I2_RIBBONP have been defined as a balanced pair.
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# Nets RIB9_P and RIB9_N have been defined as a balanced pair.
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# Nets RIB8_P and RIB8_N have been defined as a balanced pair.
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# Nets RIB7_P and RIB7_N have been defined as a balanced pair.
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# Nets RIB6_P and RIB6_N have been defined as a balanced pair.
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# Nets UNNAMED_1_CSMD0805_I70_B and UNNAMED_1_CSMD0805_I64_B have been defined as a balanced pair.
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# Nets RIB5_P and RIB5_N have been defined as a balanced pair.
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# Nets RIB4_P and RIB4_N have been defined as a balanced pair.
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# Nets RIB3_P and RIB3_N have been defined as a balanced pair.
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# Nets RIB2_P and RIB2_N have been defined as a balanced pair.
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# Nets RIB1_P and RIB1_N have been defined as a balanced pair.
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# Nets UNNAMED_1_FRONTPORTS_I2_EXTT<4> and UNNAMED_1_CSMD0603_I55_A have been defined as a balanced pair.
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# Nets UNNAMED_1_FRONTPORTS_I2_EXTT<0> and UNNAMED_1_CSMD0603_I54_B have been defined as a balanced pair.
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# Nets SMELLIE_DELAY_BUF_P and SMELLIE_DELAY_BUF_N have been defined as a balanced pair.
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# Nets CHANGE_CLK2_P and CHANGE_CLK2_N have been defined as a balanced pair.
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# Nets UNNAMED_1_FRONTPORTS_I2_LOSTA_1 and UNNAMED_1_FRONTPORTS_I2_LOSTARO have been defined as a balanced pair.
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# Nets DEF_CLK_DIVD_P and DEF_CLK_DIVD_N have been defined as a balanced pair.
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# Nets TRIG_PULS2_P and TRIG_PULS2_N have been defined as a balanced pair.
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# Nets UNNAMED_1_FRONTPORTS_I2_SMELLIE and UNNAMED_1_CSMD0603_I10_B_1 have been defined as a balanced pair.
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# Nets TRIG_PULS1_P and TRIG_PULS1_N have been defined as a balanced pair.
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# Nets UNNAMED_1_FRONTPORTS_I2_ECLTOLV and VBB_TRANS have been defined as a balanced pair.
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# Nets UNNAMED_1_MC10E116_I2_D0 and UNNAMED_1_FRONTPORTS_I2_MTCDLO have been defined as a balanced pair.
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# Nets UNNAMED_1_CHANGECLKS_I3_DEFAU_1 and UNNAMED_1_CHANGECLKS_I3_DEFAULT have been defined as a balanced pair.
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# Colormap Written to File _notify.std
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# Enter command <quit
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