707 lines
36 KiB
Plaintext
707 lines
36 KiB
Plaintext
# Cadence Design Systems, Inc.
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# Allegro PCB Router Automatic Router
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# Allegro PCB Router v16-6-112 made 2012/09/12 at 23:00:45
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# Running on host
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#
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# Command Line Parameters
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# -----------------------
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# Design File Name : C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\BSTPLC.dsn
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# Initialization options:
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# -do pasde.do
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# Status File Name : C:/Users/QGPWindowsVB/Documents/ANUSTART/worklib/tubii/physical\monitor.sts
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# -nog specified. Graphics not utilized.
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# Use Colormap In Design File.
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#
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#
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#
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#
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# do $/BSTPLC_rules.do
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define (class _difpr_DP_SYNC_2 SYNC_2_P SYNC_2_N )
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define (class _difpr_DP_USE_DEFAULT USE_DEFAULT_P USE_DEFAULT_N )
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define (class _difpr_DP_BCKP_CLK_BUFD BCKP_CLK_BUFD_P BCKP_CLK_BUFD_N )
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define (class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_GT UNNAMED_1_FRONTPORTS_I2_GTP UNNAMED_1_FRONTPORTS_I2_GTN )
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define (class _difpr_DP_TRIG_GATE1 TRIG_GATE1_P TRIG_GATE1_N )
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define (class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_SYNC24 UNNAMED_1_FRONTPORTS_I2_SYNC24P UNNAMED_1_FRONTPORTS_I2_SYNC24N )
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define (class _difpr_DP_TRIG_GATE2 TRIG_GATE2_P TRIG_GATE2_N )
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define (class _difpr_DP_USE_BCKP USE_BCKP_P USE_BCKP_N )
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define (class _difpr_DP_UNNAMED_1_CHANGECLKS_I3_CHANGECLK UNNAMED_1_CHANGECLKS_I3_CHANG_1 UNNAMED_1_CHANGECLKS_I3_CHANGEC )
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define (class _difpr_DP_UNNAMED_1_MC10E116_I1_Q0 UNNAMED_1_MC10E116_I1_Q0_1 UNNAMED_1_MC10E116_I1_Q0 )
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define (class _difpr_DP_CHOSEN_CLK CHOSEN_CLK_P CHOSEN_CLK_N )
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define (class _difpr_DP_UNNAMED_1_MC10E116_I3_Q0 UNNAMED_1_MC10E116_I3_Q0_1 UNNAMED_1_MC10E116_I3_Q0 )
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define (class _difpr_DP_UNNAMED_1_MC10E116_I1_Q3 UNNAMED_1_MC10E116_I1_Q3_1 UNNAMED_1_MC10E116_I1_Q3 )
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define (class _difpr_DP_UNNAMED_1_MC10E116_I3_Q1 UNNAMED_1_MC10E116_I3_Q1_1 UNNAMED_1_MC10E116_I3_Q1 )
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define (class _difpr_DP_UNNAMED_1_MC10E116_I4_Q0 UNNAMED_1_MC10E116_I4_Q0_1 UNNAMED_1_MC10E116_I4_Q0 )
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define (class _difpr_DP_DEF_CLK_DIV2 DEF_CLK_DIV2_P DEF_CLK_DIV2_N )
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define (class _difpr_DP_UNNAMED_1_MC10E116_I3_Q2 UNNAMED_1_MC10E116_I3_Q2_1 UNNAMED_1_MC10E116_I3_Q2 )
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define (class _difpr_DP_UNNAMED_1_MC10E116_I4_Q1 UNNAMED_1_MC10E116_I4_Q1_1 UNNAMED_1_MC10E116_I4_Q1 )
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define (class _difpr_DP_UNNAMED_1_MC10E116_I3_Q3 UNNAMED_1_MC10E116_I3_Q3_1 UNNAMED_1_MC10E116_I3_Q3 )
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define (class _difpr_DP_UNNAMED_1_MC10E116_I4_Q2 UNNAMED_1_MC10E116_I4_Q2_1 UNNAMED_1_MC10E116_I4_Q2 )
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define (class _difpr_DP_GT2_N UNNAMED_1_CAENCOMS_I8_GT2P GT2_N )
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define (class _difpr_DP_DEF_CLK_DIV4 DEF_CLK_DIV4_P DEF_CLK_DIV4_N )
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define (class _difpr_DP_UNNAMED_1_MC10E116_I4_Q3 UNNAMED_1_MC10E116_I4_Q3_1 UNNAMED_1_MC10E116_I4_Q3 )
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define (class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_RIBBONPULSEOUT UNNAMED_1_FRONTPORTS_I2_RIBBO_3 UNNAMED_1_FRONTPORTS_I2_RIBBO_2 )
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define (class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_MTCAMIMIC1OUT UNNAMED_1_FRONTPORTS_I2_MTCAM_1 UNNAMED_1_FRONTPORTS_I2_MTCAMIM )
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define (class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_MTCAMIMIC2OUT UNNAMED_1_FRONTPORTS_I2_MTCAM_4 UNNAMED_1_FRONTPORTS_I2_MTCAM_3 )
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define (class _difpr_DP_DEF_CLK_DIV8 DEF_CLK_DIV8_P DEF_CLK_DIV8_N )
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define (class _difpr_DP_CLK_BAD CLK_BAD_P CLK_BAD_N )
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define (class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_SYNC UNNAMED_1_FRONTPORTS_I2_SYNCP UNNAMED_1_FRONTPORTS_I2_SYNCN )
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define (class _difpr_DP_UNNAMED_1_CHANGECLKS_I3_DEFAULTCLK2 UNNAMED_1_CHANGECLKS_I3_DEFAU_1 UNNAMED_1_CHANGECLKS_I3_DEFAULT )
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define (class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_MTCDLO UNNAMED_1_MC10E116_I2_D0 LO_STAR_RAW )
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define (class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_ECLTOLVDSIN UNNAMED_1_FRONTPORTS_I2_ECLTOLV VBB_TRANS )
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define (class _difpr_DP_TRIG_PULS1 TRIG_PULS1_P TRIG_PULS1_N )
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define (class _difpr_DP_UNNAMED_1_CSMD0603_I10_B UNNAMED_1_FRONTPORTS_I2_SMELLIE UNNAMED_1_CSMD0603_I10_B_1 )
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define (class _difpr_DP_TRIG_PULS2 TRIG_PULS2_P TRIG_PULS2_N )
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define (class _difpr_DP_DEF_CLK_DIVD DEF_CLK_DIVD_P DEF_CLK_DIVD_N )
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define (class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_LOSTAROUT UNNAMED_1_FRONTPORTS_I2_LOSTA_1 UNNAMED_1_FRONTPORTS_I2_LOSTARO )
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define (class _difpr_DP_CHANGE_CLK2 CHANGE_CLK2_P CHANGE_CLK2_N )
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define (class _difpr_DP_SMELLIE_DELAY_BUF SMELLIE_DELAY_BUF_P SMELLIE_DELAY_BUF_N )
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define (class _difpr_DP_UNNAMED_1_CSMD0603_I54_B UNNAMED_1_FRONTPORTS_I2_EXTT<0> UNNAMED_1_CSMD0603_I54_B )
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define (class _difpr_DP_UNNAMED_1_CSMD0603_I55_A UNNAMED_1_FRONTPORTS_I2_EXTT<4> UNNAMED_1_CSMD0603_I55_A )
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define (class _difpr_DP_RIB1 RIB1_P RIB1_N )
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define (class _difpr_DP_RIB2 RIB2_P RIB2_N )
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define (class _difpr_DP_RIB3 RIB3_P RIB3_N )
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define (class _difpr_DP_RIB4 RIB4_P RIB4_N )
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define (class _difpr_DP_RIB5 RIB5_P RIB5_N )
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define (class _difpr_DP_UNNAMED_1_CSMD0805_I64_B UNNAMED_1_CSMD0805_I70_B UNNAMED_1_CSMD0805_I64_B )
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define (class _difpr_DP_RIB6 RIB6_P RIB6_N )
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define (class _difpr_DP_RIB7 RIB7_P RIB7_N )
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define (class _difpr_DP_RIB8 RIB8_P RIB8_N )
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define (class _difpr_DP_RIB9 RIB9_P RIB9_N )
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define (class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_RIBBONPULSEIN UNNAMED_1_FRONTPORTS_I2_RIBBO_1 UNNAMED_1_FRONTPORTS_I2_RIBBONP )
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define (class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_SYNC24LVDS UNNAMED_1_FRONTPORTS_I2_SYNC2_1 UNNAMED_1_FRONTPORTS_I2_SYNC24L )
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define (class _difpr_DP_UNNAMED_1_CHANGECLKS_I3_BCKPCLK2 UNNAMED_1_CHANGECLKS_I3_BCKPC_1 UNNAMED_1_CHANGECLKS_I3_BCKPCLK )
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define (class _difpr_DP_UNNAMED_1_CHANGECLKS_I3_BCKPCLK3 UNNAMED_1_CHANGECLKS_I3_BCKPC_3 UNNAMED_1_CHANGECLKS_I3_BCKPC_2 )
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define (class _difpr_DP_UNNAMED_1_MC10E116_I22_Q0 UNNAMED_1_MC10E116_I22_Q0_1 UNNAMED_1_MC10E116_I22_Q0 )
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define (class _difpr_DP_CHOSEN_CLK2 CHOSEN_CLK2_P CHOSEN_CLK2_N )
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define (class _difpr_DP_UNNAMED_1_MC10E116_I22_Q1 UNNAMED_1_MC10E116_I22_Q1_1 UNNAMED_1_MC10E116_I22_Q1 )
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define (class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_CLK100 UNNAMED_1_FRONTPORTS_I2_CLK100P UNNAMED_1_FRONTPORTS_I2_CLK100N )
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define (class _difpr_DP_SYNC24_2 SYNC24_2_P SYNC24_2_N )
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define (class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_SYNCLVDS UNNAMED_1_FRONTPORTS_I2_SYNCL_1 UNNAMED_1_FRONTPORTS_I2_SYNCLVD )
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define (class _difpr_DP_UNNAMED_1_DEFAULTCLKSEL_I1_DEFAULTCLK UNNAMED_1_DEFAULTCLKSEL_I1_BCKP UNNAMED_1_MC10E116_I1_D0 )
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define (class _difpr_DP_RIB10 RIB10_P RIB10_N )
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define (class _difpr_DP_UNNAMED_1_AD96687_I1_Q1 UNNAMED_1_AD96687_I1_Q1_1 UNNAMED_1_AD96687_I1_Q1 )
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define (class _difpr_DP_UNNAMED_1_AD96687_I1_Q2 UNNAMED_1_AD96687_I1_Q2_1 UNNAMED_1_AD96687_I1_Q2 )
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define (class _difpr_DP_TELLIE_DELAY_BUF TELLIE_DELAY_BUF_P TELLIE_DELAY_BUF_N )
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define (class _bus_LE UNNAMED_1_HCT238_I53_A0 UNNAMED_1_HCT238_I53_A1 UNNAMED_1_HCT238_I53_A2 )
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define (class _bus_COUNT_DATA_ECL COUNT_DATA_ECL<7> COUNT_DATA_ECL<6> COUNT_DATA_ECL<5> COUNT_DATA_ECL<4>
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COUNT_DATA_ECL<3> COUNT_DATA_ECL<2> COUNT_DATA_ECL<1> )
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define (class _bus_UNNAMED_1_EXTTRIGS_I70_EXTTRIGO UNNAMED_1_EXTTRIGS_I70_EXTT<15> UNNAMED_1_EXTTRIGS_I70_EXTT<14> UNNAMED_1_EXTTRIGS_I70_EXTT<13> UNNAMED_1_EXTTRIGS_I70_EXTT<12>
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UNNAMED_1_EXTTRIGS_I70_EXTT<11> UNNAMED_1_EXTTRIGS_I70_EXTT<10> UNNAMED_1_EXTTRIGS_I70_EXTTR<9> UNNAMED_1_EXTTRIGS_I70_EXTTR<8>
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UNNAMED_1_EXTTRIGS_I70_EXTTR<7> UNNAMED_1_EXTTRIGS_I70_EXTTR<6> UNNAMED_1_EXTTRIGS_I70_EXTTR<5> UNNAMED_1_EXTTRIGS_I70_EXTTR<4>
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UNNAMED_1_EXTTRIGS_I70_EXTTR<3> UNNAMED_1_EXTTRIGS_I70_EXTTR<2> UNNAMED_1_EXTTRIGS_I70_EXTTR<1> UNNAMED_1_EXTTRIGS_I70_EXTTR<0> )
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define (class _bus_CNTRL_RAW CNTRL_RAW<7> CNTRL_RAW<6> CNTRL_RAW<5> CNTRL_RAW<4>
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CNTRL_RAW<3> CNTRL_RAW<2> CNTRL_RAW<1> CNTRL_RAW<0> )
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define (class _bus_UNNAMED_1_FRONTPORTS_I2_CAENOUT UNNAMED_1_FRONTPORTS_I2_CAEN<7> UNNAMED_1_FRONTPORTS_I2_CAEN<6> UNNAMED_1_FRONTPORTS_I2_CAEN<5> UNNAMED_1_FRONTPORTS_I2_CAEN<4>
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UNNAMED_1_FRONTPORTS_I2_CAEN<3> UNNAMED_1_FRONTPORTS_I2_CAEN<2> UNNAMED_1_FRONTPORTS_I2_CAEN<1> UNNAMED_1_FRONTPORTS_I2_CAEN<0> )
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define (class _bus_BACKPLANE_OUT BACKPLANE_OUT<10> BACKPLANE_OUT<9> BACKPLANE_OUT<8> BACKPLANE_OUT<7>
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BACKPLANE_OUT<6> BACKPLANE_OUT<5> BACKPLANE_OUT<4> BACKPLANE_OUT<3>
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BACKPLANE_OUT<2> BACKPLANE_OUT<1> )
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define (class _bus_UNNAMED_1_FRONTPORTS_I2_PULSE_2 UNNAMED_1_FRONTPORTS_I2_PUL<11> UNNAMED_1_FRONTPORTS_I2_PUL<10> UNNAMED_1_FRONTPORTS_I2_PULS<9> UNNAMED_1_FRONTPORTS_I2_PULS<8>
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UNNAMED_1_FRONTPORTS_I2_PULS<7> UNNAMED_1_FRONTPORTS_I2_PULS<6> UNNAMED_1_FRONTPORTS_I2_PULS<5> UNNAMED_1_FRONTPORTS_I2_PULS<4>
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UNNAMED_1_FRONTPORTS_I2_PULS<3> UNNAMED_1_FRONTPORTS_I2_PULS<2> UNNAMED_1_FRONTPORTS_I2_PULS<1> UNNAMED_1_FRONTPORTS_I2_PULS<0> )
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define (class _bus_UNNAMED_1_FRONTPORTS_I2_SCOPEOU UNNAMED_1_FRONTPORTS_I2_SCOP<7> UNNAMED_1_FRONTPORTS_I2_SCOP<6> UNNAMED_1_FRONTPORTS_I2_SCOP<5> UNNAMED_1_FRONTPORTS_I2_SCOP<4>
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UNNAMED_1_FRONTPORTS_I2_SCOP<3> UNNAMED_1_FRONTPORTS_I2_SCOP<2> UNNAMED_1_FRONTPORTS_I2_SCOP<1> UNNAMED_1_FRONTPORTS_I2_SCOP<0> )
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define (class _bus_UNNAMED_1_FRONTPORTS_I2_EXTTRIG UNNAMED_1_FRONTPORTS_I2_EXT<15> UNNAMED_1_FRONTPORTS_I2_EXT<14> UNNAMED_1_FRONTPORTS_I2_EXT<13> UNNAMED_1_FRONTPORTS_I2_EXT<12>
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UNNAMED_1_FRONTPORTS_I2_EXT<11> UNNAMED_1_FRONTPORTS_I2_EXT<10> UNNAMED_1_FRONTPORTS_I2_EXTT<9> UNNAMED_1_FRONTPORTS_I2_EXTT<8>
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UNNAMED_1_FRONTPORTS_I2_EXTT<7> UNNAMED_1_FRONTPORTS_I2_EXTT<6> UNNAMED_1_FRONTPORTS_I2_EXTT<5> UNNAMED_1_FRONTPORTS_I2_EXTT<4>
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UNNAMED_1_FRONTPORTS_I2_EXTT<3> UNNAMED_1_FRONTPORTS_I2_EXTT<2> UNNAMED_1_FRONTPORTS_I2_EXTT<1> UNNAMED_1_FRONTPORTS_I2_EXTT<0> )
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define (class _bus_BACKPLANE_IN BACKPLANE_IN<10> BACKPLANE_IN<9> BACKPLANE_IN<8> BACKPLANE_IN<7>
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BACKPLANE_IN<6> BACKPLANE_IN<5> BACKPLANE_IN<4> BACKPLANE_IN<3>
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BACKPLANE_IN<2> BACKPLANE_IN<1> )
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define (class _bus_CAEN_BUFF_CNTRL CAEN_BUFF_CNTRL<7> CAEN_BUFF_CNTRL<6> CAEN_BUFF_CNTRL<5> CAEN_BUFF_CNTRL<4>
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CAEN_BUFF_CNTRL<3> CAEN_BUFF_CNTRL<2> CAEN_BUFF_CNTRL<1> CAEN_BUFF_CNTRL<0> )
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define (class _bus_UNNAMED_1_FRONTPORTS_I2_SCALER UNNAMED_1_FRONTPORTS_I2_SCAL<6> UNNAMED_1_FRONTPORTS_I2_SCAL<5> UNNAMED_1_FRONTPORTS_I2_SCAL<4> UNNAMED_1_FRONTPORTS_I2_SCAL<3>
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UNNAMED_1_FRONTPORTS_I2_SCAL<2> UNNAMED_1_FRONTPORTS_I2_SCAL<1> )
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define (pair (nets UNNAMED_1_FRONTPORTS_I2_SYNCP UNNAMED_1_FRONTPORTS_I2_SYNCN ))
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define (pair (nets CLK_BAD_P CLK_BAD_N ))
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define (pair (nets DEF_CLK_DIV8_P DEF_CLK_DIV8_N ))
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define (pair (nets UNNAMED_1_FRONTPORTS_I2_MTCAM_4 UNNAMED_1_FRONTPORTS_I2_MTCAM_3 ))
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define (pair (nets UNNAMED_1_FRONTPORTS_I2_MTCAM_1 UNNAMED_1_FRONTPORTS_I2_MTCAMIM ))
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define (pair (nets UNNAMED_1_FRONTPORTS_I2_RIBBO_3 UNNAMED_1_FRONTPORTS_I2_RIBBO_2 ))
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define (pair (nets UNNAMED_1_MC10E116_I4_Q3_1 UNNAMED_1_MC10E116_I4_Q3 ))
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define (pair (nets DEF_CLK_DIV4_P DEF_CLK_DIV4_N ))
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define (pair (nets UNNAMED_1_CAENCOMS_I8_GT2P GT2_N ))
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define (pair (nets UNNAMED_1_MC10E116_I4_Q2_1 UNNAMED_1_MC10E116_I4_Q2 ))
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define (pair (nets UNNAMED_1_MC10E116_I3_Q3_1 UNNAMED_1_MC10E116_I3_Q3 ))
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define (pair (nets UNNAMED_1_MC10E116_I4_Q1_1 UNNAMED_1_MC10E116_I4_Q1 ))
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define (pair (nets UNNAMED_1_MC10E116_I3_Q2_1 UNNAMED_1_MC10E116_I3_Q2 ))
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define (pair (nets DEF_CLK_DIV2_P DEF_CLK_DIV2_N ))
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define (pair (nets UNNAMED_1_MC10E116_I4_Q0_1 UNNAMED_1_MC10E116_I4_Q0 ))
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define (pair (nets UNNAMED_1_MC10E116_I3_Q1_1 UNNAMED_1_MC10E116_I3_Q1 ))
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define (pair (nets UNNAMED_1_MC10E116_I1_Q3_1 UNNAMED_1_MC10E116_I1_Q3 ))
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define (pair (nets UNNAMED_1_MC10E116_I3_Q0_1 UNNAMED_1_MC10E116_I3_Q0 ))
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define (pair (nets CHOSEN_CLK_P CHOSEN_CLK_N ))
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define (pair (nets UNNAMED_1_MC10E116_I1_Q0_1 UNNAMED_1_MC10E116_I1_Q0 ))
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define (pair (nets UNNAMED_1_CHANGECLKS_I3_CHANG_1 UNNAMED_1_CHANGECLKS_I3_CHANGEC ))
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define (pair (nets USE_BCKP_P USE_BCKP_N ))
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define (pair (nets TRIG_GATE2_P TRIG_GATE2_N ))
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define (pair (nets UNNAMED_1_FRONTPORTS_I2_SYNC24P UNNAMED_1_FRONTPORTS_I2_SYNC24N ))
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define (pair (nets TRIG_GATE1_P TRIG_GATE1_N ))
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define (pair (nets UNNAMED_1_FRONTPORTS_I2_GTP UNNAMED_1_FRONTPORTS_I2_GTN ))
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define (pair (nets BCKP_CLK_BUFD_P BCKP_CLK_BUFD_N ))
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define (pair (nets USE_DEFAULT_P USE_DEFAULT_N ))
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define (pair (nets SYNC_2_P SYNC_2_N ))
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define (pair (nets TELLIE_DELAY_BUF_P TELLIE_DELAY_BUF_N ))
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define (pair (nets UNNAMED_1_AD96687_I1_Q2_1 UNNAMED_1_AD96687_I1_Q2 ))
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define (pair (nets UNNAMED_1_AD96687_I1_Q1_1 UNNAMED_1_AD96687_I1_Q1 ))
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define (pair (nets RIB10_P RIB10_N ))
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define (pair (nets UNNAMED_1_DEFAULTCLKSEL_I1_BCKP UNNAMED_1_MC10E116_I1_D0 ))
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define (pair (nets UNNAMED_1_FRONTPORTS_I2_SYNCL_1 UNNAMED_1_FRONTPORTS_I2_SYNCLVD ))
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define (pair (nets SYNC24_2_P SYNC24_2_N ))
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define (pair (nets UNNAMED_1_FRONTPORTS_I2_CLK100P UNNAMED_1_FRONTPORTS_I2_CLK100N ))
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define (pair (nets UNNAMED_1_MC10E116_I22_Q1_1 UNNAMED_1_MC10E116_I22_Q1 ))
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define (pair (nets CHOSEN_CLK2_P CHOSEN_CLK2_N ))
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define (pair (nets UNNAMED_1_MC10E116_I22_Q0_1 UNNAMED_1_MC10E116_I22_Q0 ))
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define (pair (nets UNNAMED_1_CHANGECLKS_I3_BCKPC_3 UNNAMED_1_CHANGECLKS_I3_BCKPC_2 ))
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define (pair (nets UNNAMED_1_CHANGECLKS_I3_BCKPC_1 UNNAMED_1_CHANGECLKS_I3_BCKPCLK ))
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define (pair (nets UNNAMED_1_FRONTPORTS_I2_SYNC2_1 UNNAMED_1_FRONTPORTS_I2_SYNC24L ))
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define (pair (nets UNNAMED_1_FRONTPORTS_I2_RIBBO_1 UNNAMED_1_FRONTPORTS_I2_RIBBONP ))
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define (pair (nets RIB9_P RIB9_N ))
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define (pair (nets RIB8_P RIB8_N ))
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define (pair (nets RIB7_P RIB7_N ))
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define (pair (nets RIB6_P RIB6_N ))
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define (pair (nets UNNAMED_1_CSMD0805_I70_B UNNAMED_1_CSMD0805_I64_B ))
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|
define (pair (nets RIB5_P RIB5_N ))
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|
define (pair (nets RIB4_P RIB4_N ))
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|
define (pair (nets RIB3_P RIB3_N ))
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|
define (pair (nets RIB2_P RIB2_N ))
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|
define (pair (nets RIB1_P RIB1_N ))
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|
define (pair (nets UNNAMED_1_FRONTPORTS_I2_EXTT<4> UNNAMED_1_CSMD0603_I55_A ))
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|
define (pair (nets UNNAMED_1_FRONTPORTS_I2_EXTT<0> UNNAMED_1_CSMD0603_I54_B ))
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define (pair (nets SMELLIE_DELAY_BUF_P SMELLIE_DELAY_BUF_N ))
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define (pair (nets CHANGE_CLK2_P CHANGE_CLK2_N ))
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define (pair (nets UNNAMED_1_FRONTPORTS_I2_LOSTA_1 UNNAMED_1_FRONTPORTS_I2_LOSTARO ))
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define (pair (nets DEF_CLK_DIVD_P DEF_CLK_DIVD_N ))
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define (pair (nets TRIG_PULS2_P TRIG_PULS2_N ))
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define (pair (nets UNNAMED_1_FRONTPORTS_I2_SMELLIE UNNAMED_1_CSMD0603_I10_B_1 ))
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define (pair (nets TRIG_PULS1_P TRIG_PULS1_N ))
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define (pair (nets UNNAMED_1_FRONTPORTS_I2_ECLTOLV VBB_TRANS ))
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define (pair (nets UNNAMED_1_MC10E116_I2_D0 LO_STAR_RAW ))
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define (pair (nets UNNAMED_1_CHANGECLKS_I3_DEFAU_1 UNNAMED_1_CHANGECLKS_I3_DEFAULT ))
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rule PCB (width 7)
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rule PCB (clearance 5 (type buried_via_gap))
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|
rule PCB (clearance 7 (type wire_wire))
|
|
rule PCB (clearance 5 (type wire_smd))
|
|
rule PCB (clearance 5 (type wire_pin))
|
|
rule PCB (clearance 5 (type wire_via))
|
|
rule PCB (clearance 5 (type smd_smd))
|
|
rule PCB (clearance 5 (type smd_pin))
|
|
rule PCB (clearance 5 (type smd_via))
|
|
rule PCB (clearance 5 (type pin_pin))
|
|
rule PCB (clearance 5 (type pin_via))
|
|
rule PCB (clearance 5 (type via_via))
|
|
rule PCB (clearance 5 (type test_test))
|
|
rule PCB (clearance 5 (type test_wire))
|
|
rule PCB (clearance 5 (type test_smd))
|
|
rule PCB (clearance 5 (type test_pin))
|
|
rule PCB (clearance 5 (type test_via))
|
|
rule PCB (clearance 0 (type area_wire))
|
|
rule PCB (clearance 0 (type area_smd))
|
|
rule PCB (clearance 0 (type area_area))
|
|
rule PCB (clearance 0 (type area_pin))
|
|
rule PCB (clearance 0 (type area_via))
|
|
rule PCB (clearance 0 (type area_test))
|
|
rule PCB (clearance 5 (type microvia_microvia))
|
|
set microvia_microvia on
|
|
rule PCB (clearance 5 (type microvia_thrupin))
|
|
set microvia_thrupin on
|
|
rule PCB (clearance 5 (type microvia_smdpin))
|
|
set microvia_smdpin on
|
|
rule PCB (clearance 5 (type microvia_thruvia))
|
|
set microvia_thruvia on
|
|
rule PCB (clearance 5 (type microvia_bbvia))
|
|
set microvia_bbvia on
|
|
rule PCB (clearance 5 (type microvia_wire))
|
|
set microvia_wire on
|
|
rule PCB (clearance 5 (type bbvia_bbvia))
|
|
set bbvia_bbvia on
|
|
rule PCB (clearance 5 (type microvia_testpin))
|
|
set microvia_testpin on
|
|
rule PCB (clearance 5 (type bbvia_thrupin))
|
|
set bbvia_thrupin on
|
|
rule PCB (clearance 5 (type microvia_testvia))
|
|
set microvia_testvia on
|
|
rule PCB (clearance 5 (type bbvia_smdpin))
|
|
set bbvia_smdpin on
|
|
rule PCB (clearance 5 (type microvia_bondpad))
|
|
set microvia_bondpad on
|
|
rule PCB (clearance 5 (type bbvia_thruvia))
|
|
set bbvia_thruvia on
|
|
rule PCB (clearance 5 (type microvia_area))
|
|
set microvia_area on
|
|
rule PCB (clearance 5 (type bbvia_wire))
|
|
set bbvia_wire on
|
|
rule PCB (clearance 8 (type nhole_pin))
|
|
set nhole_pin off
|
|
rule PCB (clearance 8 (type nhole_via))
|
|
set nhole_via off
|
|
rule PCB (clearance 5 (type bbvia_area))
|
|
set bbvia_area on
|
|
rule PCB (clearance 8 (type nhole_wire))
|
|
set nhole_wire off
|
|
rule PCB (clearance 8 (type nhole_area))
|
|
set nhole_area off
|
|
rule PCB (clearance 8 (type nhole_nhole))
|
|
set nhole_nhole off
|
|
rule PCB (clearance 0 (type mhole_pin))
|
|
set mhole_pin off
|
|
rule PCB (clearance 5 (type bbvia_testpin))
|
|
set bbvia_testpin on
|
|
rule PCB (clearance 0 (type mhole_via))
|
|
set mhole_via off
|
|
rule PCB (clearance 5 (type bbvia_testvia))
|
|
set bbvia_testvia on
|
|
rule PCB (clearance 0 (type mhole_wire))
|
|
set mhole_wire off
|
|
rule PCB (clearance 0 (type mhole_area))
|
|
set mhole_area off
|
|
rule PCB (clearance 0 (type mhole_nhole))
|
|
set mhole_nhole off
|
|
rule PCB (clearance 0 (type mhole_mhole))
|
|
set mhole_mhole off
|
|
rule PCB (clearance 5 (type bbvia_bondpad))
|
|
set bbvia_bondpad on
|
|
rule PCB (clearance -1 same_net (type wire_wire))
|
|
rule PCB (clearance -1 same_net (type wire_smd))
|
|
rule PCB (clearance -1 same_net (type wire_pin))
|
|
rule PCB (clearance -1 same_net (type wire_via))
|
|
rule PCB (clearance -1 same_net (type smd_smd))
|
|
rule PCB (clearance -1 same_net (type smd_pin))
|
|
rule PCB (clearance -1 same_net (type smd_via))
|
|
rule PCB (clearance -1 same_net (type pin_pin))
|
|
rule PCB (clearance -1 same_net (type pin_via))
|
|
rule PCB (clearance -1 same_net (type via_via))
|
|
rule PCB (clearance -1 same_net (type test_test))
|
|
rule PCB (clearance -1 same_net (type test_wire))
|
|
rule PCB (clearance -1 same_net (type test_smd))
|
|
rule PCB (clearance -1 same_net (type test_pin))
|
|
rule PCB (clearance -1 same_net (type test_via))
|
|
rule PCB (clearance 0 same_net (type area_wire))
|
|
rule PCB (clearance 0 same_net (type area_smd))
|
|
rule PCB (clearance 0 same_net (type area_area))
|
|
rule PCB (clearance 0 same_net (type area_pin))
|
|
rule PCB (clearance 0 same_net (type area_via))
|
|
rule PCB (clearance 0 same_net (type area_test))
|
|
rule PCB (clearance 5 same_net (type microvia_microvia))
|
|
set microvia_microvia same_net off
|
|
rule PCB (clearance 5 same_net (type microvia_thrupin))
|
|
set microvia_thrupin same_net off
|
|
rule PCB (clearance 5 same_net (type microvia_smdpin))
|
|
set microvia_smdpin same_net off
|
|
rule PCB (clearance 5 same_net (type microvia_thruvia))
|
|
set microvia_thruvia same_net off
|
|
rule PCB (clearance 5 same_net (type microvia_bbvia))
|
|
set microvia_bbvia same_net off
|
|
rule PCB (clearance 5 same_net (type microvia_wire))
|
|
set microvia_wire same_net off
|
|
rule PCB (clearance 5 same_net (type microvia_testpin))
|
|
set microvia_testpin same_net off
|
|
rule PCB (clearance 5 same_net (type microvia_testvia))
|
|
set microvia_testvia same_net off
|
|
rule PCB (clearance 5 same_net (type microvia_bondpad))
|
|
set microvia_bondpad same_net off
|
|
rule PCB (clearance 5 same_net (type microvia_area))
|
|
set microvia_area same_net off
|
|
rule PCB (clearance 8 same_net (type nhole_pin))
|
|
set nhole_pin same_net off
|
|
rule PCB (clearance 8 same_net (type nhole_via))
|
|
set nhole_via same_net off
|
|
rule PCB (clearance 8 same_net (type nhole_wire))
|
|
set nhole_wire same_net off
|
|
rule PCB (clearance 8 same_net (type nhole_area))
|
|
set nhole_area same_net off
|
|
rule PCB (clearance 8 same_net (type nhole_nhole))
|
|
set nhole_nhole same_net off
|
|
rule PCB (clearance 5 same_net (type bbvia_bbvia))
|
|
set bbvia_bbvia same_net off
|
|
rule PCB (clearance 5 same_net (type bbvia_thrupin))
|
|
set bbvia_thrupin same_net off
|
|
rule PCB (clearance 5 same_net (type bbvia_smdpin))
|
|
set bbvia_smdpin same_net off
|
|
rule PCB (clearance 5 same_net (type bbvia_thruvia))
|
|
set bbvia_thruvia same_net off
|
|
rule PCB (clearance 5 same_net (type bbvia_wire))
|
|
set bbvia_wire same_net off
|
|
rule PCB (clearance 5 same_net (type bbvia_area))
|
|
set bbvia_area same_net off
|
|
rule PCB (clearance 5 same_net (type bbvia_testpin))
|
|
set bbvia_testpin same_net off
|
|
rule PCB (clearance 5 same_net (type bbvia_testvia))
|
|
set bbvia_testvia same_net off
|
|
rule PCB (clearance 5 same_net (type bbvia_bondpad))
|
|
set bbvia_bondpad same_net off
|
|
rule pcb (tjunction on)(junction_type all)
|
|
rule pcb (staggered_via on (min_gap 5))
|
|
rule pcb (via_at_smd off)
|
|
rule PCB (turn_under_pad off)
|
|
rule layer TOP (restricted_layer_length_factor 1)
|
|
rule layer BOTTOM (restricted_layer_length_factor 1)
|
|
rule class _difpr_DP_SYNC_2 (diffpair_line_width 7)
|
|
rule class _difpr_DP_SYNC_2 (neck_down_width 5)
|
|
define (drcv_group _DRgrp_SYNC_2_N
|
|
(drcv U17-9 U18-3 )
|
|
)
|
|
define (drcv_group _DRgrp_SYNC_2_P
|
|
(drcv U17-8 U18-4 )
|
|
)
|
|
define (drcv_groupset _DRgrpset_SYNC_2_N_SYNC_2_P _DRgrp_SYNC_2_N _DRgrp_SYNC_2_P)
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|
rule class _difpr_DP_USE_DEFAULT (diffpair_line_width 7)
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|
rule class _difpr_DP_USE_DEFAULT (neck_down_width 5)
|
|
rule class _difpr_DP_BCKP_CLK_BUFD (diffpair_line_width 7)
|
|
rule class _difpr_DP_BCKP_CLK_BUFD (neck_down_width 5)
|
|
rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_GT (diffpair_line_width 7)
|
|
rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_GT (neck_down_width 5)
|
|
define (drcv_group _DRgrp_UNNAMED_1_FRONTPORTS_I2_GTN
|
|
(drcv R192-2 U17-24 )
|
|
)
|
|
define (drcv_group _DRgrp_UNNAMED_1_FRONTPORTS_I2_GTP
|
|
(drcv R191-2 U17-27 )
|
|
)
|
|
define (drcv_groupset _DRgrpset_UNNAMED_1_FRONTPORTS_I2_GTN_UNNAMED_1_FRONTPORTS_I2_GTP _DRgrp_UNNAMED_1_FRONTPORTS_I2_GTN _DRgrp_UNNAMED_1_FRONTPORTS_I2_GTP)
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|
rule class _difpr_DP_TRIG_GATE1 (diffpair_line_width 7)
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|
rule class _difpr_DP_TRIG_GATE1 (neck_down_width 5)
|
|
define (drcv_group _DRgrp_TRIG_GATE1_N
|
|
(drcv U44-13 U45-3 )
|
|
)
|
|
define (drcv_group _DRgrp_TRIG_GATE1_P
|
|
(drcv U44-12 U45-4 )
|
|
)
|
|
define (drcv_groupset _DRgrpset_TRIG_GATE1_N_TRIG_GATE1_P _DRgrp_TRIG_GATE1_N _DRgrp_TRIG_GATE1_P)
|
|
rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_SYNC24 (diffpair_line_width 7)
|
|
rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_SYNC24 (neck_down_width 5)
|
|
define (drcv_group _DRgrp_UNNAMED_1_FRONTPORTS_I2_SYNC24N
|
|
(drcv R190-2 U17-6 )
|
|
)
|
|
define (drcv_group _DRgrp_UNNAMED_1_FRONTPORTS_I2_SYNC24P
|
|
(drcv R189-2 U17-5 )
|
|
)
|
|
define (drcv_groupset _DRgrpset_UNNAMED_1_FRONTPORTS_I2_SYNC24N_UNNAMED_1_FRONTPORTS_I2_SYNC24P _DRgrp_UNNAMED_1_FRONTPORTS_I2_SYNC24N _DRgrp_UNNAMED_1_FRONTPORTS_I2_SYNC24P)
|
|
rule class _difpr_DP_TRIG_GATE2 (diffpair_line_width 7)
|
|
rule class _difpr_DP_TRIG_GATE2 (neck_down_width 5)
|
|
define (drcv_group _DRgrp_TRIG_GATE2_N
|
|
(drcv U44-15 U45-8 )
|
|
)
|
|
define (drcv_group _DRgrp_TRIG_GATE2_P
|
|
(drcv U44-14 U45-9 )
|
|
)
|
|
define (drcv_groupset _DRgrpset_TRIG_GATE2_N_TRIG_GATE2_P _DRgrp_TRIG_GATE2_N _DRgrp_TRIG_GATE2_P)
|
|
rule class _difpr_DP_USE_BCKP (diffpair_line_width 7)
|
|
rule class _difpr_DP_USE_BCKP (neck_down_width 5)
|
|
rule class _difpr_DP_UNNAMED_1_CHANGECLKS_I3_CHANGECLK (diffpair_line_width 7)
|
|
rule class _difpr_DP_UNNAMED_1_CHANGECLKS_I3_CHANGECLK (neck_down_width 5)
|
|
rule class _difpr_DP_UNNAMED_1_MC10E116_I1_Q0 (diffpair_line_width 7)
|
|
rule class _difpr_DP_UNNAMED_1_MC10E116_I1_Q0 (neck_down_width 5)
|
|
rule class _difpr_DP_CHOSEN_CLK (diffpair_line_width 7)
|
|
rule class _difpr_DP_CHOSEN_CLK (neck_down_width 5)
|
|
rule class _difpr_DP_UNNAMED_1_MC10E116_I3_Q0 (diffpair_line_width 7)
|
|
rule class _difpr_DP_UNNAMED_1_MC10E116_I3_Q0 (neck_down_width 5)
|
|
rule class _difpr_DP_UNNAMED_1_MC10E116_I1_Q3 (diffpair_line_width 7)
|
|
rule class _difpr_DP_UNNAMED_1_MC10E116_I1_Q3 (neck_down_width 5)
|
|
define (drcv_group _DRgrp_UNNAMED_1_MC10E116_I1_Q3
|
|
(drcv U17-18 U18-13 )
|
|
)
|
|
define (drcv_group _DRgrp_UNNAMED_1_MC10E116_I1_Q3_1
|
|
(drcv U17-17 U18-14 )
|
|
)
|
|
define (drcv_groupset _DRgrpset_UNNAMED_1_MC10E116_I1_Q3_UNNAMED_1_MC10E116_I1_Q3_1 _DRgrp_UNNAMED_1_MC10E116_I1_Q3 _DRgrp_UNNAMED_1_MC10E116_I1_Q3_1)
|
|
rule class _difpr_DP_UNNAMED_1_MC10E116_I3_Q1 (diffpair_line_width 7)
|
|
rule class _difpr_DP_UNNAMED_1_MC10E116_I3_Q1 (neck_down_width 5)
|
|
rule class _difpr_DP_UNNAMED_1_MC10E116_I4_Q0 (diffpair_line_width 7)
|
|
rule class _difpr_DP_UNNAMED_1_MC10E116_I4_Q0 (neck_down_width 5)
|
|
rule class _difpr_DP_DEF_CLK_DIV2 (diffpair_line_width 7)
|
|
rule class _difpr_DP_DEF_CLK_DIV2 (neck_down_width 5)
|
|
rule class _difpr_DP_UNNAMED_1_MC10E116_I3_Q2 (diffpair_line_width 7)
|
|
rule class _difpr_DP_UNNAMED_1_MC10E116_I3_Q2 (neck_down_width 5)
|
|
rule class _difpr_DP_UNNAMED_1_MC10E116_I4_Q1 (diffpair_line_width 7)
|
|
rule class _difpr_DP_UNNAMED_1_MC10E116_I4_Q1 (neck_down_width 5)
|
|
rule class _difpr_DP_UNNAMED_1_MC10E116_I3_Q3 (diffpair_line_width 7)
|
|
rule class _difpr_DP_UNNAMED_1_MC10E116_I3_Q3 (neck_down_width 5)
|
|
rule class _difpr_DP_UNNAMED_1_MC10E116_I4_Q2 (diffpair_line_width 7)
|
|
rule class _difpr_DP_UNNAMED_1_MC10E116_I4_Q2 (neck_down_width 5)
|
|
rule class _difpr_DP_GT2_N (diffpair_line_width 7)
|
|
rule class _difpr_DP_GT2_N (neck_down_width 5)
|
|
rule class _difpr_DP_DEF_CLK_DIV4 (diffpair_line_width 7)
|
|
rule class _difpr_DP_DEF_CLK_DIV4 (neck_down_width 5)
|
|
rule class _difpr_DP_UNNAMED_1_MC10E116_I4_Q3 (diffpair_line_width 7)
|
|
rule class _difpr_DP_UNNAMED_1_MC10E116_I4_Q3 (neck_down_width 5)
|
|
rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_RIBBONPULSEOUT (diffpair_line_width 7)
|
|
rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_RIBBONPULSEOUT (neck_down_width 5)
|
|
rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_MTCAMIMIC1OUT (diffpair_line_width 7)
|
|
rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_MTCAMIMIC1OUT (neck_down_width 5)
|
|
rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_MTCAMIMIC2OUT (diffpair_line_width 7)
|
|
rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_MTCAMIMIC2OUT (neck_down_width 5)
|
|
rule class _difpr_DP_DEF_CLK_DIV8 (diffpair_line_width 7)
|
|
rule class _difpr_DP_DEF_CLK_DIV8 (neck_down_width 5)
|
|
rule class _difpr_DP_CLK_BAD (diffpair_line_width 7)
|
|
rule class _difpr_DP_CLK_BAD (neck_down_width 5)
|
|
rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_SYNC (diffpair_line_width 7)
|
|
rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_SYNC (neck_down_width 5)
|
|
define (drcv_group _DRgrp_UNNAMED_1_FRONTPORTS_I2_SYNCN
|
|
(drcv R188-2 U17-4 )
|
|
)
|
|
define (drcv_group _DRgrp_UNNAMED_1_FRONTPORTS_I2_SYNCP
|
|
(drcv R187-2 U17-3 )
|
|
)
|
|
define (drcv_groupset _DRgrpset_UNNAMED_1_FRONTPORTS_I2_SYNCN_UNNAMED_1_FRONTPORTS_I2_SYNCP _DRgrp_UNNAMED_1_FRONTPORTS_I2_SYNCN _DRgrp_UNNAMED_1_FRONTPORTS_I2_SYNCP)
|
|
rule class _difpr_DP_UNNAMED_1_CHANGECLKS_I3_DEFAULTCLK2 (diffpair_line_width 7)
|
|
rule class _difpr_DP_UNNAMED_1_CHANGECLKS_I3_DEFAULTCLK2 (neck_down_width 5)
|
|
rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_MTCDLO (diffpair_line_width 7)
|
|
rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_MTCDLO (neck_down_width 5)
|
|
define (drcv_group _DRgrp_LO_STAR_RAW
|
|
(drcv U12-4 U11-27 )
|
|
(drcv U12-4 U11-5 )
|
|
(drcv U12-3 U11-27 )
|
|
)
|
|
define (drcv_group _DRgrp_UNNAMED_1_MC10E116_I2_D0
|
|
(drcv U11-2 U11-28 )
|
|
(drcv U11-2 U11-6 )
|
|
(drcv U11-2 U11-4 )
|
|
)
|
|
define (drcv_groupset _DRgrpset_LO_STAR_RAW_UNNAMED_1_MC10E116_I2_D0 _DRgrp_LO_STAR_RAW _DRgrp_UNNAMED_1_MC10E116_I2_D0)
|
|
rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_ECLTOLVDSIN (diffpair_line_width 7)
|
|
rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_ECLTOLVDSIN (neck_down_width 5)
|
|
define (drcv_group _DRgrp_VBB_TRANS
|
|
(drcv U55-2 U55-26 )
|
|
)
|
|
define (drcv_group _DRgrp_UNNAMED_1_FRONTPORTS_I2_ECLTOLV
|
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(drcv R101-2 U55-5 )
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)
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define (drcv_groupset _DRgrpset_VBB_TRANS_UNNAMED_1_FRONTPORTS_I2_ECLTOLV _DRgrp_VBB_TRANS _DRgrp_UNNAMED_1_FRONTPORTS_I2_ECLTOLV)
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rule class _difpr_DP_TRIG_PULS1 (diffpair_line_width 7)
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rule class _difpr_DP_TRIG_PULS1 (neck_down_width 5)
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define (drcv_group _DRgrp_TRIG_PULS1_N
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(drcv U46-4 U43-26 )
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)
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define (drcv_group _DRgrp_TRIG_PULS1_P
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(drcv U46-3 U43-25 )
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)
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define (drcv_groupset _DRgrpset_TRIG_PULS1_N_TRIG_PULS1_P _DRgrp_TRIG_PULS1_N _DRgrp_TRIG_PULS1_P)
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rule class _difpr_DP_UNNAMED_1_CSMD0603_I10_B (diffpair_line_width 7)
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rule class _difpr_DP_UNNAMED_1_CSMD0603_I10_B (neck_down_width 5)
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rule class _difpr_DP_TRIG_PULS2 (diffpair_line_width 7)
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rule class _difpr_DP_TRIG_PULS2 (neck_down_width 5)
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define (drcv_group _DRgrp_TRIG_PULS2_N
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(drcv U46-18 U43-24 )
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)
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define (drcv_group _DRgrp_TRIG_PULS2_P
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(drcv U46-19 U43-23 )
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)
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define (drcv_groupset _DRgrpset_TRIG_PULS2_N_TRIG_PULS2_P _DRgrp_TRIG_PULS2_N _DRgrp_TRIG_PULS2_P)
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rule class _difpr_DP_DEF_CLK_DIVD (diffpair_line_width 7)
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rule class _difpr_DP_DEF_CLK_DIVD (neck_down_width 5)
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rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_LOSTAROUT (diffpair_line_width 7)
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rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_LOSTAROUT (neck_down_width 5)
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rule class _difpr_DP_CHANGE_CLK2 (diffpair_line_width 7)
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rule class _difpr_DP_CHANGE_CLK2 (neck_down_width 5)
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rule class _difpr_DP_SMELLIE_DELAY_BUF (diffpair_line_width 7)
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rule class _difpr_DP_SMELLIE_DELAY_BUF (neck_down_width 5)
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rule class _difpr_DP_UNNAMED_1_CSMD0603_I54_B (diffpair_line_width 7)
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rule class _difpr_DP_UNNAMED_1_CSMD0603_I54_B (neck_down_width 5)
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rule class _difpr_DP_UNNAMED_1_CSMD0603_I55_A (diffpair_line_width 7)
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rule class _difpr_DP_UNNAMED_1_CSMD0603_I55_A (neck_down_width 5)
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rule class _difpr_DP_RIB1 (diffpair_line_width 7)
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rule class _difpr_DP_RIB1 (neck_down_width 5)
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define (drcv_group _DRgrp_RIB1_N
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(drcv U52-3 U53-1 )
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)
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define (drcv_group _DRgrp_RIB1_P
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(drcv U52-4 U53-2 )
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)
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define (drcv_groupset _DRgrpset_RIB1_N_RIB1_P _DRgrp_RIB1_N _DRgrp_RIB1_P)
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rule class _difpr_DP_RIB2 (diffpair_line_width 7)
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rule class _difpr_DP_RIB2 (neck_down_width 5)
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define (drcv_group _DRgrp_RIB2_N
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(drcv R95-2 U54-1 )
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)
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define (drcv_group _DRgrp_RIB2_P
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(drcv R94-2 U54-2 )
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)
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define (drcv_groupset _DRgrpset_RIB2_N_RIB2_P _DRgrp_RIB2_N _DRgrp_RIB2_P)
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rule class _difpr_DP_RIB3 (diffpair_line_width 7)
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rule class _difpr_DP_RIB3 (neck_down_width 5)
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define (drcv_group _DRgrp_RIB3_N
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(drcv U51-3 U54-3 )
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)
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define (drcv_group _DRgrp_RIB3_P
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(drcv U51-4 U54-4 )
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)
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define (drcv_groupset _DRgrpset_RIB3_N_RIB3_P _DRgrp_RIB3_N _DRgrp_RIB3_P)
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rule class _difpr_DP_RIB4 (diffpair_line_width 7)
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rule class _difpr_DP_RIB4 (neck_down_width 5)
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define (drcv_group _DRgrp_RIB4_N
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(drcv U53-3 U52-12 )
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)
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define (drcv_group _DRgrp_RIB4_P
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(drcv U53-4 U52-13 )
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)
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define (drcv_groupset _DRgrpset_RIB4_N_RIB4_P _DRgrp_RIB4_N _DRgrp_RIB4_P)
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rule class _difpr_DP_RIB5 (diffpair_line_width 7)
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rule class _difpr_DP_RIB5 (neck_down_width 5)
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define (drcv_group _DRgrp_RIB5_N
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(drcv U52-8 U53-5 )
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)
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define (drcv_group _DRgrp_RIB5_P
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(drcv U52-9 U53-6 )
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)
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define (drcv_groupset _DRgrpset_RIB5_N_RIB5_P _DRgrp_RIB5_N _DRgrp_RIB5_P)
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rule class _difpr_DP_UNNAMED_1_CSMD0805_I64_B (diffpair_line_width 7)
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rule class _difpr_DP_UNNAMED_1_CSMD0805_I64_B (neck_down_width 5)
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define (drcv_group _DRgrp_UNNAMED_1_CSMD0805_I64_B
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(drcv U43-2 U43-6 )
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)
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|
define (drcv_group _DRgrp_UNNAMED_1_CSMD0805_I70_B
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(drcv C59-2 U43-5 )
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|
)
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|
define (drcv_groupset _DRgrpset_UNNAMED_1_CSMD0805_I64_B_UNNAMED_1_CSMD0805_I70_B _DRgrp_UNNAMED_1_CSMD0805_I64_B _DRgrp_UNNAMED_1_CSMD0805_I70_B)
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rule class _difpr_DP_RIB6 (diffpair_line_width 7)
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rule class _difpr_DP_RIB6 (neck_down_width 5)
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|
define (drcv_group _DRgrp_RIB6_N
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(drcv U54-5 U51-12 )
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)
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|
define (drcv_group _DRgrp_RIB6_P
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|
(drcv U54-6 U51-13 )
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|
)
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define (drcv_groupset _DRgrpset_RIB6_N_RIB6_P _DRgrp_RIB6_N _DRgrp_RIB6_P)
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rule class _difpr_DP_RIB7 (diffpair_line_width 7)
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rule class _difpr_DP_RIB7 (neck_down_width 5)
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define (drcv_group _DRgrp_RIB7_N
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|
(drcv U51-8 U54-7 )
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|
)
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|
define (drcv_group _DRgrp_RIB7_P
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|
(drcv U51-9 U54-8 )
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|
)
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|
define (drcv_groupset _DRgrpset_RIB7_N_RIB7_P _DRgrp_RIB7_N _DRgrp_RIB7_P)
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rule class _difpr_DP_RIB8 (diffpair_line_width 7)
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rule class _difpr_DP_RIB8 (neck_down_width 5)
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define (drcv_group _DRgrp_RIB8_N
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|
(drcv U53-7 U52-15 )
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|
)
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|
define (drcv_group _DRgrp_RIB8_P
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|
(drcv R92-2 U53-8 )
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|
)
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|
define (drcv_groupset _DRgrpset_RIB8_N_RIB8_P _DRgrp_RIB8_N _DRgrp_RIB8_P)
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rule class _difpr_DP_RIB9 (diffpair_line_width 7)
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rule class _difpr_DP_RIB9 (neck_down_width 5)
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|
define (drcv_group _DRgrp_RIB9_N
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|
(drcv U52-18 U53-9 )
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|
)
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|
define (drcv_group _DRgrp_RIB9_P
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|
(drcv U52-19 U53-10 )
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|
)
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|
define (drcv_groupset _DRgrpset_RIB9_N_RIB9_P _DRgrp_RIB9_N _DRgrp_RIB9_P)
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|
rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_RIBBONPULSEIN (diffpair_line_width 7)
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|
rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_RIBBONPULSEIN (neck_down_width 5)
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|
define (drcv_group _DRgrp_UNNAMED_1_FRONTPORTS_I2_RIBBONP
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|
(drcv R89-2 U52-5 )
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|
)
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|
define (drcv_group _DRgrp_UNNAMED_1_FRONTPORTS_I2_RIBBO_1
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|
(drcv R88-2 U52-7 )
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|
)
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|
define (drcv_groupset _DRgrpset_UNNAMED_1_FRONTPORTS_I2_RIBBONP_UNNAMED_1_FRONTPORTS_I2_RIBBO_1 _DRgrp_UNNAMED_1_FRONTPORTS_I2_RIBBONP _DRgrp_UNNAMED_1_FRONTPORTS_I2_RIBBO_1)
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rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_SYNC24LVDS (diffpair_line_width 7)
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|
rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_SYNC24LVDS (neck_down_width 5)
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|
rule class _difpr_DP_UNNAMED_1_CHANGECLKS_I3_BCKPCLK2 (diffpair_line_width 7)
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|
rule class _difpr_DP_UNNAMED_1_CHANGECLKS_I3_BCKPCLK2 (neck_down_width 5)
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|
rule class _difpr_DP_UNNAMED_1_CHANGECLKS_I3_BCKPCLK3 (diffpair_line_width 7)
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|
rule class _difpr_DP_UNNAMED_1_CHANGECLKS_I3_BCKPCLK3 (neck_down_width 5)
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|
rule class _difpr_DP_UNNAMED_1_MC10E116_I22_Q0 (diffpair_line_width 7)
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|
rule class _difpr_DP_UNNAMED_1_MC10E116_I22_Q0 (neck_down_width 5)
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|
define (drcv_group _DRgrp_UNNAMED_1_MC10E116_I22_Q0
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|
(drcv U55-8 U56-4 )
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|
)
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|
define (drcv_group _DRgrp_UNNAMED_1_MC10E116_I22_Q0_1
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|
(drcv U55-9 U56-3 )
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|
)
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|
define (drcv_groupset _DRgrpset_UNNAMED_1_MC10E116_I22_Q0_UNNAMED_1_MC10E116_I22_Q0_1 _DRgrp_UNNAMED_1_MC10E116_I22_Q0 _DRgrp_UNNAMED_1_MC10E116_I22_Q0_1)
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rule class _difpr_DP_CHOSEN_CLK2 (diffpair_line_width 7)
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|
rule class _difpr_DP_CHOSEN_CLK2 (neck_down_width 5)
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|
rule class _difpr_DP_UNNAMED_1_MC10E116_I22_Q1 (diffpair_line_width 7)
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|
rule class _difpr_DP_UNNAMED_1_MC10E116_I22_Q1 (neck_down_width 5)
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|
define (drcv_group _DRgrp_UNNAMED_1_MC10E116_I22_Q1
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|
(drcv U55-11 U56-9 )
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|
)
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|
define (drcv_group _DRgrp_UNNAMED_1_MC10E116_I22_Q1_1
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|
(drcv U55-12 U56-8 )
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|
)
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|
define (drcv_groupset _DRgrpset_UNNAMED_1_MC10E116_I22_Q1_UNNAMED_1_MC10E116_I22_Q1_1 _DRgrp_UNNAMED_1_MC10E116_I22_Q1 _DRgrp_UNNAMED_1_MC10E116_I22_Q1_1)
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|
rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_CLK100 (diffpair_line_width 7)
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|
rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_CLK100 (neck_down_width 5)
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|
rule class _difpr_DP_SYNC24_2 (diffpair_line_width 7)
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|
rule class _difpr_DP_SYNC24_2 (neck_down_width 5)
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|
define (drcv_group _DRgrp_SYNC24_2_N
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|
(drcv U17-12 U18-8 )
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|
)
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|
define (drcv_group _DRgrp_SYNC24_2_P
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|
(drcv U17-11 U18-9 )
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|
)
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|
define (drcv_groupset _DRgrpset_SYNC24_2_N_SYNC24_2_P _DRgrp_SYNC24_2_N _DRgrp_SYNC24_2_P)
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|
rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_SYNCLVDS (diffpair_line_width 7)
|
|
rule class _difpr_DP_UNNAMED_1_FRONTPORTS_I2_SYNCLVDS (neck_down_width 5)
|
|
rule class _difpr_DP_UNNAMED_1_DEFAULTCLKSEL_I1_DEFAULTCLK (diffpair_line_width 7)
|
|
rule class _difpr_DP_UNNAMED_1_DEFAULTCLKSEL_I1_DEFAULTCLK (neck_down_width 5)
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|
rule class _difpr_DP_RIB10 (diffpair_line_width 7)
|
|
rule class _difpr_DP_RIB10 (neck_down_width 5)
|
|
define (drcv_group _DRgrp_RIB10_N
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|
(drcv U54-9 U51-15 )
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|
)
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|
define (drcv_group _DRgrp_RIB10_P
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|
(drcv U54-10 U51-17 )
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|
)
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|
define (drcv_groupset _DRgrpset_RIB10_N_RIB10_P _DRgrp_RIB10_N _DRgrp_RIB10_P)
|
|
rule class _difpr_DP_UNNAMED_1_AD96687_I1_Q1 (diffpair_line_width 7)
|
|
rule class _difpr_DP_UNNAMED_1_AD96687_I1_Q1 (neck_down_width 5)
|
|
define (drcv_group _DRgrp_UNNAMED_1_AD96687_I1_Q1
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|
(drcv R48-2 U39-5 )
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|
)
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|
define (drcv_group _DRgrp_UNNAMED_1_AD96687_I1_Q1_1
|
|
(drcv R46-2 U39-8 )
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|
)
|
|
define (drcv_groupset _DRgrpset_UNNAMED_1_AD96687_I1_Q1_UNNAMED_1_AD96687_I1_Q1_1 _DRgrp_UNNAMED_1_AD96687_I1_Q1 _DRgrp_UNNAMED_1_AD96687_I1_Q1_1)
|
|
rule class _difpr_DP_UNNAMED_1_AD96687_I1_Q2 (diffpair_line_width 7)
|
|
rule class _difpr_DP_UNNAMED_1_AD96687_I1_Q2 (neck_down_width 5)
|
|
define (drcv_group _DRgrp_UNNAMED_1_AD96687_I1_Q2
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|
(drcv R45-2 U39-13 )
|
|
)
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|
define (drcv_group _DRgrp_UNNAMED_1_AD96687_I1_Q2_1
|
|
(drcv R43-2 U39-15 )
|
|
)
|
|
define (drcv_groupset _DRgrpset_UNNAMED_1_AD96687_I1_Q2_UNNAMED_1_AD96687_I1_Q2_1 _DRgrp_UNNAMED_1_AD96687_I1_Q2 _DRgrp_UNNAMED_1_AD96687_I1_Q2_1)
|
|
rule class _difpr_DP_TELLIE_DELAY_BUF (diffpair_line_width 7)
|
|
rule class _difpr_DP_TELLIE_DELAY_BUF (neck_down_width 5)
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|
write colormap _notify.std
|
|
# do C:/Users/QGPWIN~1/AppData/Local/Temp/#Taaaaas02200.tmp
|
|
unselect all routing
|
|
select component Q2
|
|
select component L1
|
|
select component L2
|
|
select component L4
|
|
select component Q3
|
|
select component Q4
|
|
set route_diagonal 4
|
|
grid wire 0.100000 (direction x) (offset 0.000000)
|
|
grid wire 0.100000 (direction y) (offset 0.000000)
|
|
grid via 0.100000 (direction x) (offset 0.000000)
|
|
grid via 0.100000 (direction y) (offset 0.000000)
|
|
protect all wires
|
|
direction TOP horizontal
|
|
select layer TOP
|
|
unprotect layer_wires TOP
|
|
direction BOTTOM vertical
|
|
select layer BOTTOM
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|
unprotect layer_wires BOTTOM
|
|
cost via -1
|
|
set turbo_stagger off
|
|
limit outside -1
|
|
rule pcb (patterns_allowed trombone accordion)
|
|
set pattern_stacking on
|
|
rule pcb (sawtooth_amplitude -1 -1)
|
|
rule pcb (sawtooth_gap -1)
|
|
rule pcb (accordion_amplitude -1 -1)
|
|
rule pcb (accordion_gap -1)
|
|
rule pcb (trombone_run_length -1)
|
|
rule pcb (trombone_gap -1)
|
|
unprotect selected
|
|
smart_route (auto_fanout off) (auto_testpoint off) (auto_miter on)
|
|
write routes (changed_only) (reset_changed) C:/Users/QGPWIN~1/AppData/Local/Temp/#Taaaaat02200.tmp
|
|
quit -c
|