4.4 KiB
4.4 KiB
1 | FILE_TYPE = CONNECTIVITY; |
---|---|
2 | {Allegro Design Entry HDL 16.6-p007 (v16-6-112F) 10/10/2012} |
3 | ; |
4 | TRIM |
5 | VOUT |
6 | GND |
7 | TEMP |
8 | VIN |
9 | ; |
10 | A<0> |
11 | B<0> |
12 | ; |
13 | B<0> |
14 | A<0> |
15 | ; |
16 | B<0> |
17 | A<0> |
18 | ; |
19 | A<0> |
20 | B<0> |
21 | ; |
22 | B<0> |
23 | A<0> |
24 | ; |
25 | B<0> |
26 | A<0> |
27 | ; |
28 | B<0> |
29 | A<0> |
30 | ; |
31 | V+ |
32 | TRIM_A |
33 | IN+ |
34 | IN- |
35 | OUT |
36 | V- |
37 | TRIM_B |
38 | ; |
39 | B<0> |
40 | A<0> |
41 | ; |
42 | A |
43 | ; |
44 | A<0> |
45 | B<0> |
46 | END. |