Tubii_Tk2/worklib/vref_gen/sch_1/page1.csv
2015-06-04 15:18:08 -04:00

4.4 KiB

1FILE_TYPE = CONNECTIVITY;
2{Allegro Design Entry HDL 16.6-p007 (v16-6-112F) 10/10/2012}
3;
4TRIM
5VOUT
6GND
7TEMP
8VIN
9;
10A<0>
11B<0>
12;
13B<0>
14A<0>
15;
16B<0>
17A<0>
18;
19A<0>
20B<0>
21;
22B<0>
23A<0>
24;
25B<0>
26A<0>
27;
28B<0>
29A<0>
30;
31V+
32TRIM_A
33IN+
34IN-
35OUT
36V-
37TRIM_B
38;
39B<0>
40A<0>
41;
42A
43;
44A<0>
45B<0>
46END.