bac-hardware/bacbus/README.md
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# bacBus v4r1
`bacBus` is a custom M.2-based Key-M interconnect standard used to connect subsystems within the **Build a CubeSat** (BAC) architecture.
The system is designed to have two largely identical and independent buses: **bacBus A** on the Ym side and **bacBus B** on the Yp side. The buses can be used for redundancy or for independent capabilities, such as dedicating an entire bus to payload operations. This adds flexibility to the architecture.
The currently available boards support a single bacBus only, with the exception of the EPS, which supports both A and B. Due to the symmetrical nature of the architecture, boards can be connected to either bus. Future iterations will include dual-bacBus capable boards.
The BAC architecture supports a 5mm PCB pitch, hence the interconnect boards are made lengths of 12.5mm to 52.5mm with increments of 5mm:
- 12.5mm
- 17.5mm
- 22.5mm
- 27.5mm
- 32.5mm
- 37.5mm
- 42.5mm
- 47.5mm
- 52.5mm
Longer lengths are possible (feel free to open an [issue](https://codeberg.org/buildacubesat-project/bac-hardware/issues)). KiCad projects for the currently available lengths can be found in the [interconnect folder](https://codeberg.org/buildacubesat-project/bac-hardware/src/branch/main/bacbus/interconnect/), Gerber files are available in the [releases tab](https://codeberg.org/buildacubesat-project/bac-hardware/releases).
To reach from the EPS to the first board on the Zm side, the 32.5mm long interconnect is adequate. Single-bacBus PCBs offer a passthrough on the unconnected side the same can be implemented on custom boards or models. For PCB-to-PCB distances of less than 5mm, the use of common board-to-board connectors is recommended (pin headers, mezzanine connectors). Search the [structure repo release section](https://codeberg.org/buildacubesat-project/bac-structure/releases) for "PCB", "Mezzanine" and "Module Volume" for starting points.
![bacBus Assembly Render](./bacbus-assembly-render.webp)
---
## Key Changes in v4r1
Version **v4r1** introduces a simplified and more robust system architecture with **CAN-based intra-satellite communication**, improved **power distribution**, and additional **system-wide control and safety signals**.
### Redundant CAN architecture
* All intra-sat communication now uses **dual redundant CAN buses**
* Legacy buses (I2C, SPI, etc.) have been removed from the interconnect
* CAN routing has been optimized for node placement and signal integrity
### Improved power distribution
* **VBAT is now exposed for power delivery**, not only voltage sensing
* Improved routing for **power rails on the EPS**
* Dedicated auxiliary rail support
### System-wide control signals
Several control and status signals were added to simplify system coordination:
* `EPS_OK`: indicates EPS rails are enabled and nominal
* `SAFE_MODE`: forces nodes into safe configuration
* `3V3_AUX_EN`: enables auxiliary 3.3V rail
* `HDRM_EN`: enables hold-down release mechanism deployment
* `RF_EN`: enables RF subsystems
* `PAYLOAD_EN`: enables payload subsystem
### Timing synchronization
* `SYNC_PULSE` provides a **system-wide timing reference** for timestamp synchronization.
### Redundant deployment detection
* A second deployment switch group `DEPLOY_SW_2` provides redundancy.
---
## Pinout
### Table
| Pin number | Pin name | Type | Bus domain | Notes |
| --- | --- | --- | --- | --- |
| 1 | <span style="background-color:#6f8fbf; padding:4px 6px; border-radius:4px;">CAN_1_H</span> | Differential signal | per bus | Primary CAN bus 1, high |
| 2 | <span style="background-color:#6f8fbf; padding:4px 6px; border-radius:4px;">CAN_1_L</span> | Differential signal | per bus | Primary CAN bus 1, low |
| 3, 4 | <span style="background-color:#9e9e9e; padding:4px 6px; border-radius:4px;">GND</span> | Ground | shared | Return path |
| 5 | <span style="background-color:#6f8fbf; padding:4px 6px; border-radius:4px;">CAN_2_H</span> | Differential signal | per bus | Secondary CAN bus 2, high |
| 6 | <span style="background-color:#6f8fbf; padding:4px 6px; border-radius:4px;">CAN_2_L</span> | Differential signal | per bus | Secondary CAN bus 2, low |
| 7, 8 | <span style="background-color:#9e9e9e; padding:4px 6px; border-radius:4px;">GND</span> | Ground | shared | Return path |
| 9 | <span style="background-color:#bfa34a; padding:4px 6px; border-radius:4px;">EPS_OK</span> | Flag / status | per bus | Main power rails status flag |
| 10 | <span style="background-color:#bfa34a; padding:4px 6px; border-radius:4px;">SYNC_PULSE</span> | Control / timing | shared | System-wide timestamp sync |
| 11 | <span style="background-color:#bfa34a; padding:4px 6px; border-radius:4px;">SAFE_MODE</span> | Flag / status | shared | System safe-mode control |
| 12 | <span style="background-color:#bfa34a; padding:4px 6px; border-radius:4px;">3V3_AUX_EN</span> | Control / power | per bus | Auxiliary 3.3V enable |
| 13 | <span style="background-color:#bfa34a; padding:4px 6px; border-radius:4px;">HDRM_EN</span> | Control / inhibit | shared | Hold-down release enable |
| 14 | <span style="background-color:#bfa34a; padding:4px 6px; border-radius:4px;">RF_EN</span> | Control / inhibit | shared | RF subsystem enable |
| 15 | <span style="background-color:#bfa34a; padding:4px 6px; border-radius:4px;">PAYLOAD_EN</span> | Control / payload | per bus | Payload power / enable control |
| 16-23 | <span style="background-color:#59c959; padding:4px 6px; border-radius:4px;">GPIO 1-8</span> | GPIO | per bus | User-defined |
| 24-29 | <span style="background-color:#c96b6b; padding:4px 6px; border-radius:4px;">3V3_MAIN</span> | Power | per bus | Main 3.3V rail |
| 30-34 | <span style="background-color:#9e9e9e; padding:4px 6px; border-radius:4px;">GND</span> | Ground | shared | Return path |
| 35 | <span style="background-color:#c96b6b; padding:4px 6px; border-radius:4px;">3V3_AUX</span> | Power | shared | Auxiliary 3.3V rail |
| 36-37 | <span style="background-color:#9e9e9e; padding:4px 6px; border-radius:4px;">GND</span> | Ground | shared | Return path |
| 38-41 | <span style="background-color:#c96b6b; padding:4px 6px; border-radius:4px;">VBAT</span> | Power | shared | Battery rail, exposed for power and sense |
| 42-43 | <span style="background-color:#9e9e9e; padding:4px 6px; border-radius:4px;">GND</span> | Ground | shared | Return path |
| 44 | <span style="background-color:#bfa34a; padding:4px 6px; border-radius:4px;">RBF</span> | Flag / inhibit | shared | High: Remove-before-flight pin removed |
| 45 | <span style="background-color:#bfa34a; padding:4px 6px; border-radius:4px;">DEPLOY_SW_1</span> | Flag / inhibit | shared | High: Deployment switch group 1 open |
| 46 | <span style="background-color:#bfa34a; padding:4px 6px; border-radius:4px;">DEPLOY_SW_2</span> | Flag / inhibit | shared | High: Deployment switch group 2 open |
| 47-49 | <span style="background-color:#b0a7c9; padding:4px 6px; border-radius:4px;">RESERVED 1-3</span> | Reserved | per bus | Do not use |
| 50-57 | <span style="background-color:#59c959; padding:4px 6px; border-radius:4px;">GPIO 9-16</span> | GPIO | per bus | User-defined |
| 58-63 | <span style="background-color:#9e9e9e; padding:4px 6px; border-radius:4px;">GND</span> | Ground | shared | Return path |
| 64-67 | <span style="background-color:#c96b6b; padding:4px 6px; border-radius:4px;">5V_MAIN</span> | Power | per bus | Main 5V rail |
### Diagram
![bacBus Assembly Render](./bacbus-v4r1-pinout.webp)
---
## Reference Files
The following files are provided to simplify hardware design using bacBus.
### Pinout definition
- [bacBus-v4r1-pinout.pdf](./bacBus-v4r1-pinout.pdf)
- [bacBus-v4r1-pinout.csv](./bacBus-v4r1-pinout.csv)
Contains the full pin definition including signal descriptions and electrical constraints.
### Pin-to-position lookup table
- [bacBus-v4r1-pin-lut.csv](./bacBus-v4r1-pin-lut.csv)
Provides mappings between:
- bacBus pin numbers
- connector pin number
- schematic net names
- hierarchical label names
This simplifies schematic integration and automated symbol generation.
### KiKit panel configuration
- [interconnect-panel-4x4-kikit-conf.json](./interconnect-panel-4x4-kikit-conf.json)
KiKit configuration for panelizing **bacBus interconnect boards**.
---
## KiCad Integration
Updated **KiCad symbol and footprint presets** for bacBus will be provided soon.
These will likely be released alongside the **KiCad 10** update.