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313 lines
12 KiB
Verilog
313 lines
12 KiB
Verilog
/*
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File: axi_elink_if.v
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This file is part of the Parallella FPGA Reference Design.
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Roman Trogan <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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`include "fpga_constants.v"
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module axi_elink_if (/*AUTOARG*/
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// Outputs
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reset_chip, reset_fpga, emaxi_access_outb, emaxi_write_outb,
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emaxi_datamode_outb, emaxi_ctrlmode_outb, emaxi_dstaddr_outb,
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emaxi_srcaddr_outb, emaxi_data_outb, emaxi_wr_wait_outb,
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esaxi_access_outb, esaxi_write_outb, esaxi_datamode_outb,
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esaxi_ctrlmode_outb, esaxi_dstaddr_outb, esaxi_srcaddr_outb,
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esaxi_data_outb, esaxi_wr_wait_outb, esaxi_rd_wait_outb,
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elink_access_outb, elink_write_outb, elink_datamode_outb,
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elink_ctrlmode_outb, elink_dstaddr_outb, elink_srcaddr_outb,
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elink_data_outb, elink_wr_wait_outb, elink_rd_wait_outb,
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elink_disable, elink_cclk_enb, elink_clk_div,
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// Inputs
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eclk, aclk, reset, emaxi_access_inb, emaxi_write_inb,
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emaxi_datamode_inb, emaxi_ctrlmode_inb, emaxi_dstaddr_inb,
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emaxi_srcaddr_inb, emaxi_data_inb, emaxi_wr_wait_inb,
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emaxi_rd_wait_inb, esaxi_access_inb, esaxi_write_inb,
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esaxi_datamode_inb, esaxi_ctrlmode_inb, esaxi_dstaddr_inb,
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esaxi_srcaddr_inb, esaxi_data_inb, esaxi_wr_wait_inb,
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esaxi_rd_wait_inb, elink_access_inb, elink_write_inb,
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elink_datamode_inb, elink_ctrlmode_inb, elink_dstaddr_inb,
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elink_srcaddr_inb, elink_data_inb, elink_wr_wait_inb,
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elink_rd_wait_inb
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);
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//#########
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//# Inputs
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//#########
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input eclk;
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input aclk;
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input reset;
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//##############################
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//# From axi_master
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//##############################
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input emaxi_access_inb;
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input emaxi_write_inb;
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input [1:0] emaxi_datamode_inb;
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input [3:0] emaxi_ctrlmode_inb;
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input [31:0] emaxi_dstaddr_inb;
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input [31:0] emaxi_srcaddr_inb;
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input [31:0] emaxi_data_inb;
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input emaxi_wr_wait_inb;
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input emaxi_rd_wait_inb;
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//##############################
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//# From axi_slave
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//##############################
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input esaxi_access_inb;
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input esaxi_write_inb;
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input [1:0] esaxi_datamode_inb;
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input [3:0] esaxi_ctrlmode_inb;
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input [31:0] esaxi_dstaddr_inb;
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input [31:0] esaxi_srcaddr_inb;
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input [31:0] esaxi_data_inb;
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input esaxi_wr_wait_inb;
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input esaxi_rd_wait_inb;
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//##############################
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//# From elink
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//##############################
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input elink_access_inb;
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input elink_write_inb;
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input [1:0] elink_datamode_inb;
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input [3:0] elink_ctrlmode_inb;
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input [31:0] elink_dstaddr_inb;
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input [31:0] elink_srcaddr_inb;
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input [31:0] elink_data_inb;
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input elink_wr_wait_inb;
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input elink_rd_wait_inb;
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//##########
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//# Outputs
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//##########
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output reset_chip;
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output reset_fpga;
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//##############################
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//# To axi_master
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//##############################
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output emaxi_access_outb;
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output emaxi_write_outb;
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output [1:0] emaxi_datamode_outb;
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output [3:0] emaxi_ctrlmode_outb;
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output [31:0] emaxi_dstaddr_outb;
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output [31:0] emaxi_srcaddr_outb;
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output [31:0] emaxi_data_outb;
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output emaxi_wr_wait_outb;
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//##############################
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//# To axi_slave
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//##############################
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output esaxi_access_outb;
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output esaxi_write_outb;
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output [1:0] esaxi_datamode_outb;
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output [3:0] esaxi_ctrlmode_outb;
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output [31:0] esaxi_dstaddr_outb;
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output [31:0] esaxi_srcaddr_outb;
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output [31:0] esaxi_data_outb;
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output esaxi_wr_wait_outb;
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output esaxi_rd_wait_outb;
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//##############################
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//# To elink
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//##############################
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output elink_access_outb;
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output elink_write_outb;
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output [1:0] elink_datamode_outb;
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output [3:0] elink_ctrlmode_outb;
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output [31:0] elink_dstaddr_outb;
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output [31:0] elink_srcaddr_outb;
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output [31:0] elink_data_outb;
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output elink_wr_wait_outb;
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output elink_rd_wait_outb;
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// controls
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output elink_disable;
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output elink_cclk_enb;
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output [1:0] elink_clk_div;
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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//#########
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//# Regs
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//#########
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reg esaxi_access_en;
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//#########
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//# Wires
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//#########
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wire emaxi_sel;
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wire route_to_slave;
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wire axi_access_in;
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wire axi_write_in;
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wire [1:0] axi_datamode_in;
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wire [3:0] axi_ctrlmode_in;
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wire [31:0] axi_dstaddr_in;
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wire [31:0] axi_srcaddr_in;
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wire [31:0] axi_data_in;
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wire axi_wr_wait_in;
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wire axi_rd_wait_in;
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wire axi_access_out;
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wire axi_write_out;
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wire [1:0] axi_datamode_out;
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wire [3:0] axi_ctrlmode_out;
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wire [31:0] axi_dstaddr_out;
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wire [31:0] axi_srcaddr_out;
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wire [31:0] axi_data_out;
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wire axi_wr_wait_out;
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wire axi_rd_wait_out;
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//###################################
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//# FPGACFG Instantiation
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//###################################
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/*fpgacfg AUTO_TEMPLATE (.elink_\(.*\)_in (elink_\1_inb[]),
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.elink_\(.*\)_out (elink_\1_outb[]),
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.axi_\(.*\)_in (axi_\1_in[]),
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.axi_\(.*\)_out (axi_\1_out[]),
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);
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*/
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fpgacfg fpgacfg
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(/*AUTOINST*/
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// Outputs
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.reset_chip (reset_chip),
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.reset_fpga (reset_fpga),
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.elink_access_out (elink_access_outb), // Templated
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.elink_write_out (elink_write_outb), // Templated
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.elink_datamode_out (elink_datamode_outb[1:0]), // Templated
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.elink_ctrlmode_out (elink_ctrlmode_outb[3:0]), // Templated
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.elink_dstaddr_out (elink_dstaddr_outb[31:0]), // Templated
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.elink_srcaddr_out (elink_srcaddr_outb[31:0]), // Templated
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.elink_data_out (elink_data_outb[31:0]), // Templated
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.elink_wr_wait_out (elink_wr_wait_outb), // Templated
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.elink_rd_wait_out (elink_rd_wait_outb), // Templated
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.elink_disable (elink_disable),
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.elink_cclk_enb (elink_cclk_enb),
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.elink_clk_div (elink_clk_div[1:0]),
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.axi_access_out (axi_access_out), // Templated
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.axi_write_out (axi_write_out), // Templated
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.axi_datamode_out (axi_datamode_out[1:0]), // Templated
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.axi_ctrlmode_out (axi_ctrlmode_out[3:0]), // Templated
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.axi_dstaddr_out (axi_dstaddr_out[31:0]), // Templated
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.axi_srcaddr_out (axi_srcaddr_out[31:0]), // Templated
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.axi_data_out (axi_data_out[31:0]), // Templated
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.axi_wr_wait_out (axi_wr_wait_out), // Templated
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.axi_rd_wait_out (axi_rd_wait_out), // Templated
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// Inputs
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.eclk (eclk),
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.aclk (aclk),
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.reset (reset),
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.elink_access_in (elink_access_inb), // Templated
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.elink_write_in (elink_write_inb), // Templated
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.elink_datamode_in (elink_datamode_inb[1:0]), // Templated
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.elink_ctrlmode_in (elink_ctrlmode_inb[3:0]), // Templated
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.elink_dstaddr_in (elink_dstaddr_inb[31:0]), // Templated
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.elink_srcaddr_in (elink_srcaddr_inb[31:0]), // Templated
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.elink_data_in (elink_data_inb[31:0]), // Templated
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.elink_wr_wait_in (elink_wr_wait_inb), // Templated
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.elink_rd_wait_in (elink_rd_wait_inb), // Templated
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.axi_access_in (axi_access_in), // Templated
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.axi_write_in (axi_write_in), // Templated
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.axi_datamode_in (axi_datamode_in[1:0]), // Templated
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.axi_ctrlmode_in (axi_ctrlmode_in[3:0]), // Templated
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.axi_dstaddr_in (axi_dstaddr_in[31:0]), // Templated
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.axi_srcaddr_in (axi_srcaddr_in[31:0]), // Templated
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.axi_data_in (axi_data_in[31:0]), // Templated
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.axi_wr_wait_in (axi_wr_wait_in), // Templated
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.axi_rd_wait_in (axi_rd_wait_in)); // Templated
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//####################################
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//# Transactions from- AXI to- ELINK
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//####################################
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//# arbitration
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always @ (posedge eclk or posedge reset)
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if(reset)
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esaxi_access_en <= 1'b0;
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else
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esaxi_access_en <= ~esaxi_access_en;
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assign esaxi_wr_wait_outb = emaxi_access_inb & ~esaxi_access_en |
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axi_wr_wait_out;
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assign esaxi_rd_wait_outb = emaxi_access_inb & ~esaxi_access_en |
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axi_rd_wait_out;
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assign emaxi_wr_wait_outb = esaxi_access_inb & esaxi_access_en |
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axi_wr_wait_out;
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assign emaxi_sel = emaxi_access_inb & ~emaxi_wr_wait_outb;
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//# selection mux
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assign axi_access_in = emaxi_access_inb | esaxi_access_inb;
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assign axi_write_in = emaxi_sel ? emaxi_write_inb :
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esaxi_write_inb;
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assign axi_datamode_in[1:0] = emaxi_sel ? emaxi_datamode_inb[1:0]:
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esaxi_datamode_inb[1:0];
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assign axi_ctrlmode_in[3:0] = emaxi_sel ? emaxi_ctrlmode_inb[3:0]:
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esaxi_ctrlmode_inb[3:0];
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assign axi_dstaddr_in[31:0] = emaxi_sel ? emaxi_dstaddr_inb[31:0]:
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esaxi_dstaddr_inb[31:0];
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assign axi_srcaddr_in[31:0] = emaxi_sel ? emaxi_srcaddr_inb[31:0]:
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esaxi_srcaddr_inb[31:0];
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assign axi_data_in[31:0] = emaxi_sel ? emaxi_data_inb[31:0]:
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esaxi_data_inb[31:0];
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//####################################
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//# Transactions from- ELINK to- AXI
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//####################################
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//# AXI Slave port has a predefined read source address of `AXI_COORD
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assign route_to_slave = (axi_dstaddr_out[31:20] == `AXI_COORD);
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assign esaxi_access_outb = axi_access_out & route_to_slave;
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assign emaxi_access_outb = axi_access_out & ~route_to_slave;
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assign esaxi_write_outb = axi_write_out;
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assign esaxi_datamode_outb[1:0] = axi_datamode_out[1:0];
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assign esaxi_ctrlmode_outb[3:0] = axi_ctrlmode_out[3:0];
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assign esaxi_dstaddr_outb[31:0] = axi_dstaddr_out[31:0];
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assign esaxi_srcaddr_outb[31:0] = axi_srcaddr_out[31:0];
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assign esaxi_data_outb[31:0] = axi_data_out[31:0];
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assign emaxi_write_outb = axi_write_out;
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assign emaxi_datamode_outb[1:0] = axi_datamode_out[1:0];
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assign emaxi_ctrlmode_outb[3:0] = axi_ctrlmode_out[3:0];
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assign emaxi_dstaddr_outb[31:0] = axi_dstaddr_out[31:0];
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assign emaxi_srcaddr_outb[31:0] = axi_srcaddr_out[31:0];
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assign emaxi_data_outb[31:0] = axi_data_out[31:0];
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assign axi_wr_wait_in = route_to_slave & esaxi_wr_wait_inb |
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~route_to_slave & emaxi_wr_wait_inb;
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assign axi_rd_wait_in = route_to_slave & esaxi_rd_wait_inb |
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~route_to_slave & emaxi_rd_wait_inb;
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endmodule // axi_elink_if
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// Local Variables:
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// verilog-library-directories:("." "../elink" "../parallella-I")
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// End:
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