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349 lines
13 KiB
Verilog
349 lines
13 KiB
Verilog
/*
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File: axi_slave.v
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This file is part of the Parallella FPGA Reference Design.
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Roman Trogan <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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module axi_slave (/*AUTOARG*/
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// Outputs
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csysack, cactive, awready, wready, bid, bresp, bvalid, arready,
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rid, rdata, rresp, rlast, rvalid, emesh_access_inb,
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emesh_write_inb, emesh_datamode_inb, emesh_ctrlmode_inb,
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emesh_dstaddr_inb, emesh_srcaddr_inb, emesh_data_inb,
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emesh_wr_wait_inb, emesh_rd_wait_inb,
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// Inputs
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aclk, eclk, reset, csysreq, awid, awaddr, awlen, awsize, awburst,
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awlock, awcache, awprot, awvalid, wid, wdata, wstrb, wlast, wvalid,
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bready, arid, araddr, arlen, arsize, arburst, arlock, arcache,
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arprot, arvalid, rready, emesh_access_outb, emesh_write_outb,
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emesh_datamode_outb, emesh_ctrlmode_outb, emesh_dstaddr_outb,
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emesh_srcaddr_outb, emesh_data_outb, emesh_wr_wait_outb,
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emesh_rd_wait_outb, awqos, arqos
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);
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parameter SIDW = 12; //ID Width
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parameter SAW = 32; //Address Bus Width
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parameter SDW = 32; //Data Bus Width
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//#########
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//# Inputs
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//#########
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// global signals
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input aclk; // clock source of the axi bus
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input eclk; // clock source of emesh interface
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input reset; // reset
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input csysreq;// system exit low-power state request
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//########################
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//# Write address channel
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//########################
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input [SIDW-1:0] awid; //write address ID
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input [SAW-1:0] awaddr; //write address
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input [3:0] awlen; //burst lenght (the number of data transfers)
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input [2:0] awsize; //burst size (the size of each transfer)
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input [1:0] awburst; //burst type
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input [1:0] awlock; //lock type (atomic characteristics)
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input [3:0] awcache; //memory type
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input [2:0] awprot; //protection type
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input awvalid; //write address valid
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//########################
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//# Write data channel
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//########################
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input [SIDW-1:0] wid; //write ID tag (supported only in AXI3)
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input [SDW-1:0] wdata; //write data
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input [3:0] wstrb; //write strobes
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input wlast; //write last. Indicates the last transfer in burst
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input wvalid;//write valid
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//########################
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// Write response channel
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//########################
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input bready;//response ready
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//########################
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//# Read address channel
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//########################
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input [SIDW-1:0] arid; //read address ID
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input [SAW-1:0] araddr; //read address
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input [3:0] arlen; //burst lenght (the number of data transfers)
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input [2:0] arsize; //burst size (the size of each transfer)
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input [1:0] arburst; //burst type
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input [1:0] arlock; //lock type (atomic characteristics)
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input [3:0] arcache; //memory type
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input [2:0] arprot; //protection type
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input arvalid; //write address valid
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//########################
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//# Read data channel
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//########################
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input rready; //read ready
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//##############################
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//# From the emesh interface
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//##############################
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input emesh_access_outb;
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input emesh_write_outb;
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input [1:0] emesh_datamode_outb;
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input [3:0] emesh_ctrlmode_outb;
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input [31:0] emesh_dstaddr_outb;
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input [31:0] emesh_srcaddr_outb;
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input [31:0] emesh_data_outb;
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input emesh_wr_wait_outb;
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input emesh_rd_wait_outb;
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//##########
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//# Outputs
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//##########
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// global signals
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output csysack;//exit low-power state acknowledgement
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output cactive;//clock active
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//########################
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//# Write address channel
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//########################
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output awready; //write address ready
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//########################
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//# Write data channel
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//########################
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output wready; //write ready
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//########################
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// Write response channel
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//########################
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output [SIDW-1:0] bid; //response ID tag
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output [1:0] bresp; //write response
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output bvalid;//write response valid
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//########################
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//# Read address channel
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//########################
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output arready;//read address ready
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//########################
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//# Read data channel
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//########################
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output [SIDW-1:0] rid; //read ID tag (must match arid of the transaction)
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output [SDW-1:0] rdata; //read data
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output [1:0] rresp; //read response
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output rlast; //read last, indicates the last transfer in burst
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output rvalid;//read valid
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//##############################
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//# To the emesh interface
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//##############################
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output emesh_access_inb;
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output emesh_write_inb;
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output [1:0] emesh_datamode_inb;
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output [3:0] emesh_ctrlmode_inb;
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output [31:0] emesh_dstaddr_inb;
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output [31:0] emesh_srcaddr_inb;
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output [31:0] emesh_data_inb;
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output emesh_wr_wait_inb;
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output emesh_rd_wait_inb;
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//#######################################################################
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//# The following feature are not supported (AXI4 only)
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//# If un-commented, those signals have to be driven with default values
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//#######################################################################
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input [3:0] awqos; //Quality of Service (AXI4 only) default 4'b0000
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// input [3:0] awregion;//region identifier (AXI4 only)
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// input awuser; //user signal (AXI4 only)
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// input wuser; //user signal (AXI4 only)
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input [3:0] arqos; //quality of service (AXI4 only) default 4'b0000
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// input [3:0] arregion;//region identifier (AXI4 only)
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// input aruser; //user signal (AXI4 only)
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// output buser; //user signal (AXI4 only)
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// output ruser; //user signal (AXI4 only)
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//#########
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//# Regs
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//#########
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reg csysack;
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//#########
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//# Wires
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//#########
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wire emesh_wr_access_inb;
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wire emesh_wr_write_inb;
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wire [1:0] emesh_wr_datamode_inb;
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wire [3:0] emesh_wr_ctrlmode_inb;
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wire [31:0] emesh_wr_dstaddr_inb;
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wire [31:0] emesh_wr_srcaddr_inb;
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wire [31:0] emesh_wr_data_inb;
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wire emesh_rd_access_inb;
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wire emesh_rd_write_inb;
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wire [1:0] emesh_rd_datamode_inb;
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wire [3:0] emesh_rd_ctrlmode_inb;
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wire [31:0] emesh_rd_dstaddr_inb;
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wire [31:0] emesh_rd_srcaddr_inb;
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wire [31:0] emesh_rd_data_inb;
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wire emesh_rd_wait;
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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//##################################################
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//# This block doesn't accept read transactions
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//# from emesh.
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//##################################################
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assign emesh_rd_wait_inb = 1'b0;
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//##################################################
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//# Low Power State
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//# We don't support low power state
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//##################################################
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assign cactive = 1'b1;
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always @ (posedge eclk or posedge reset)
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if(reset)
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csysack <= 1'b1;
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else
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csysack <= csysreq;
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//##################################################
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//# RD/WR transaction selection
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//# *Write transactions are of the higher priority
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//##################################################
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assign emesh_rd_wait = emesh_rd_wait_outb | emesh_wr_access_inb;
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assign emesh_access_inb = emesh_wr_access_inb | emesh_rd_access_inb;
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assign emesh_write_inb = emesh_wr_access_inb ? emesh_wr_write_inb :
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emesh_rd_write_inb;
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assign emesh_datamode_inb[1:0] = emesh_wr_access_inb ?
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emesh_wr_datamode_inb[1:0] :
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emesh_rd_datamode_inb[1:0];
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assign emesh_ctrlmode_inb[3:0] = emesh_wr_access_inb ?
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emesh_wr_ctrlmode_inb[3:0] :
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emesh_rd_ctrlmode_inb[3:0];
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assign emesh_dstaddr_inb[31:0] = emesh_wr_access_inb ?
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emesh_wr_dstaddr_inb[31:0] :
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emesh_rd_dstaddr_inb[31:0];
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assign emesh_srcaddr_inb[31:0] = emesh_wr_access_inb ?
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emesh_wr_srcaddr_inb[31:0] :
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emesh_rd_srcaddr_inb[31:0];
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assign emesh_data_inb[31:0] = emesh_wr_access_inb ?
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emesh_wr_data_inb[31:0] :
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emesh_rd_data_inb[31:0];
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//##################################
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//# Slave Write Port Instantiation
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//##################################
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/*axi_slave_wr AUTO_TEMPLATE(.emesh_wr_wait_outb (emesh_wr_wait_outb),
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.emesh_\(.*\)_inb (emesh_wr_\1_inb[]),
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);
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*/
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axi_slave_wr axi_slave_wr(/*AUTOINST*/
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// Outputs
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.awready (awready),
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.wready (wready),
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.bid (bid[SIDW-1:0]),
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.bresp (bresp[1:0]),
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.bvalid (bvalid),
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.emesh_access_inb (emesh_wr_access_inb), // Templated
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.emesh_write_inb (emesh_wr_write_inb), // Templated
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.emesh_datamode_inb(emesh_wr_datamode_inb[1:0]), // Templated
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.emesh_ctrlmode_inb(emesh_wr_ctrlmode_inb[3:0]), // Templated
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.emesh_dstaddr_inb (emesh_wr_dstaddr_inb[31:0]), // Templated
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.emesh_srcaddr_inb (emesh_wr_srcaddr_inb[31:0]), // Templated
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.emesh_data_inb (emesh_wr_data_inb[31:0]), // Templated
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// Inputs
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.aclk (aclk),
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.eclk (eclk),
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.reset (reset),
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.awid (awid[SIDW-1:0]),
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.awaddr (awaddr[SAW-1:0]),
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.awlen (awlen[3:0]),
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.awsize (awsize[2:0]),
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.awburst (awburst[1:0]),
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.awlock (awlock[1:0]),
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.awcache (awcache[3:0]),
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.awprot (awprot[2:0]),
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.awvalid (awvalid),
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.wid (wid[SIDW-1:0]),
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.wdata (wdata[SDW-1:0]),
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.wstrb (wstrb[3:0]),
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.wlast (wlast),
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.wvalid (wvalid),
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.bready (bready),
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.emesh_wr_wait_outb(emesh_wr_wait_outb)); // Templated
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//##################################
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//# Slave Read Port Instantiation
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//##################################
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/*axi_slave_rd AUTO_TEMPLATE(.emesh_rd_wait_outb (emesh_rd_wait),
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.emesh_wr_wait_inb (emesh_wr_wait_inb),
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.emesh_\(.*\)_inb (emesh_rd_\1_inb[]),
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);
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*/
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axi_slave_rd axi_slave_rd(/*AUTOINST*/
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// Outputs
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.arready (arready),
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.rid (rid[SIDW-1:0]),
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.rdata (rdata[SDW-1:0]),
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.rresp (rresp[1:0]),
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.rlast (rlast),
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.rvalid (rvalid),
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.emesh_access_inb (emesh_rd_access_inb), // Templated
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.emesh_write_inb (emesh_rd_write_inb), // Templated
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.emesh_datamode_inb(emesh_rd_datamode_inb[1:0]), // Templated
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.emesh_ctrlmode_inb(emesh_rd_ctrlmode_inb[3:0]), // Templated
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.emesh_dstaddr_inb (emesh_rd_dstaddr_inb[31:0]), // Templated
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.emesh_srcaddr_inb (emesh_rd_srcaddr_inb[31:0]), // Templated
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.emesh_data_inb (emesh_rd_data_inb[31:0]), // Templated
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.emesh_wr_wait_inb (emesh_wr_wait_inb), // Templated
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// Inputs
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.aclk (aclk),
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.eclk (eclk),
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.reset (reset),
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.arid (arid[SIDW-1:0]),
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.araddr (araddr[SAW-1:0]),
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.arlen (arlen[3:0]),
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.arsize (arsize[2:0]),
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.arburst (arburst[1:0]),
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.arlock (arlock[1:0]),
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.arcache (arcache[3:0]),
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.arprot (arprot[2:0]),
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.arvalid (arvalid),
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.rready (rready),
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.emesh_access_outb (emesh_access_outb),
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.emesh_write_outb (emesh_write_outb),
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.emesh_datamode_outb(emesh_datamode_outb[1:0]),
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.emesh_ctrlmode_outb(emesh_ctrlmode_outb[3:0]),
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.emesh_dstaddr_outb(emesh_dstaddr_outb[31:0]),
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.emesh_srcaddr_outb(emesh_srcaddr_outb[31:0]),
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.emesh_data_outb (emesh_data_outb[31:0]),
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.emesh_rd_wait_outb(emesh_rd_wait)); // Templated
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endmodule // axi_slave
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