uob-hep-pc072/hardware/Cadence/top/archive_libs/oxflib
Peter Hastings 79075ed892 854S01AKILF Hidden symbol pins!
Hi, not too sure you will be happy with my workaround for this but whoever made the schematic symbol has hidden the power and gnd pins. GND is fine but the "VDD" rail will not short to the 3V3 provided. I have altered settings within Concept HDL to let me use a synonym (which does work but not on the logical net set by the symbol) to short the 3.3V and VDD but it doesn't work. I have used a ferrite bead to join the voltages together and some bypass caps.
2024-06-26 11:17:31 +01:00
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08_#20timing__arc/sch_1 timing sheet archived in oxflib component folder 2024-06-21 14:31:16 +01:00
header2x1 first item added 2024-06-19 09:44:37 +01:00
kkcon3 second item completed 2024-06-19 10:05:30 +01:00
sf#2d0603fp015f#2d2 Two items left to implement 2024-06-21 10:23:04 +01:00
sf#2d0603s300#2d2 another snapshot 2024-06-19 11:18:54 +01:00
shf#2d105#2d01#2dl#2dd#2dsm Two items left to implement 2024-06-21 10:23:04 +01:00
ss16fp Mux task remains 2024-06-21 11:39:15 +01:00
synonym 854S01AKILF Hidden symbol pins! 2024-06-26 11:17:31 +01:00