David Cussans b97093f169 Used new version of Cadence DE-HDL to export to PDF (retaining properties, rather than printing to PS then converting). Moved all components under project ( rather than in ../../../../library and edited cds.lib accordingly		2025-01-23 13:19:18 +00:00
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cfg_package	Changed port definitions for SFP_DATA and PLL on timing and FPGA blocks	2023-01-27 12:49:21 +00:00
cfg_pic	Changed port definitions for SFP_DATA and PLL on timing and FPGA blocks	2023-01-27 12:49:21 +00:00
cfg_verilog	Changed port definitions for SFP_DATA and PLL on timing and FPGA blocks	2023-01-27 12:49:21 +00:00
cfg_vhdl	Changed port definitions for SFP_DATA and PLL on timing and FPGA blocks	2023-01-27 12:49:21 +00:00
entity	Hierarchy sorted - net names fixed	2024-07-03 07:34:36 +01:00
physical	Changed port definitions for SFP_DATA and PLL on timing and FPGA blocks	2023-01-27 12:49:21 +00:00
sch_1	Used new version of Cadence DE-HDL to export to PDF (retaining properties, rather than printing to PS then converting). Moved all components under project ( rather than in ../../../../library and edited cds.lib accordingly	2025-01-23 13:19:18 +00:00
sym_1	Hierarchy sorted - net names fixed	2024-07-03 07:34:36 +01:00