This website requires JavaScript.
Explore
Sign In
AllSpiceMirrors
/
uob-hep-pc072
Watch
4
Fork
1
You've already forked uob-hep-pc072
mirror of
https://github.com/uob-hep-cad/uob-hep-pc072.git
synced
2026-07-15 16:09:51 +00:00
Files
Issues
Releases
Files
main
uob-hep-pc072
/
hardware
/
Cadence
/
top
/
temp
/
xxnedtmp5
History
Magnus Loutit
6fda5b3b76
Modified schematic to rename output busses of DC/DC converter modules. They were both VO<1..0>, which meant they were connected together. Renamed to VO_3V3<1..0> and VO_2V5<1..0> to keep them separate.
2023-03-16 13:17:03 +00:00
..
undo1
Modified schematic to rename output busses of DC/DC converter modules. They were both VO<1..0>, which meant they were connected together. Renamed to VO_3V3<1..0> and VO_2V5<1..0> to keep them separate.
2023-03-16 13:17:03 +00:00
