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mirror of https://github.com/uob-hep-cad/uob-hep-pc072.git synced 2025-09-09 18:33:49 +00:00
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uob-hep-pc072/hardware/Cadence/top/temp/xxnedtmp6
History
Magnus Loutit 4261c60210 Edited stackup to fit PCBTrain's bog-standard 10 layer stackup. Adjusted diff pair track widths and spacings to get 100R diff impedances on layers Top, 3, 7, 9 & BOTTOM. Saved stackup details because Allegro keeps losing the info if it crashes before you save the .brd file.
2023-03-20 18:36:08 +00:00
..
undo1
placing ancilliary components to 3V3 DC/DC converter
2023-03-17 15:22:46 +00:00
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