Tubii_Tk2/Parts/parts/misc/ds90lv027/entity/verilog.v

// generated by newgenasym  Mon Mar 02 15:48:32 2015


module ds90lv027 (d1, d2, gnd, q1, \q1* , q2, \q2* , vcc);
    input d1;
    input d2;
    input gnd;
    output q1;
    output \q1* ;
    output q2;
    output \q2* ;
    input vcc;


    initial
        begin
        end

endmodule