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  • 5125f196c2 Clarifying naming restriction -design files are creative common -rights reserved to all trademark names Andreas Olofsson 2016-02-03 10:56:51 -0500
  • d2bb97e527 Adding incomplete parallella-rf board -Uses AD9361 -Started by Fred Huettig Andreas Olofsson 2016-02-03 10:47:42 -0500
  • 8624a02974 Adding 4K core board -Initial concept, "should work" -Comments appreciated! Andreas Olofsson 2016-02-03 10:37:53 -0500
  • 7be223f896 Adding PCI-104 Parallella board -Work in progress, more news later -Comments appreciated! Andreas Olofsson 2016-02-03 10:24:35 -0500
  • 06d4daa9be Clarified LICENSE terms -removed reference to GPL -added creative common Andreas Olofsson 2016-02-03 00:53:53 -0500
  • 046706db8a Reorg Andreas Olofsson 2016-02-03 00:43:14 -0500
  • 6582046c79 Added logo Andreas Olofsson 2015-06-24 13:00:15 -0400
  • 79eac7b9a5 Resizing Andreas Olofsson 2015-06-24 12:40:17 -0400
  • dd10c4f887 Adding smaller logo Andreas Olofsson 2015-06-24 12:36:46 -0400
  • 66515b516f Adding docs directory for images and other general stuff Each board/project should be self contained Andreas Olofsson 2015-06-24 12:29:52 -0400
  • beb4ca09e9 Add ESDK 2015.1 compatible bitstreams 2015.1 Ola Jeppsson 2015-05-23 22:36:09 +0200
  • 9fb9d9f6fb Milestone: WRITE AND READ FROM HOST WORKS! Andreas Olofsson 2015-04-21 17:16:20 -0400
  • e17b144a86 Adding test for readback from host Andreas Olofsson 2015-04-21 17:15:56 -0400
  • 7256088f68 Bug fix, missing pipeline stage on read response -Apparantly old FIFO was not pipelined (IE data comes back same cycle). -Not knowing the Xilinx logic, I made it a regular one cycle pipeline memory based FIFO Andreas Olofsson 2015-04-21 17:14:30 -0400
  • 5548b35de0 Added wait signal for reads Andreas Olofsson 2015-04-21 17:13:53 -0400
  • e08e63beee Implemented enesh memory -not parametrized -keeping 64 bit wide for now Andreas Olofsson 2015-04-21 17:13:09 -0400
  • b51a532fde Rename Andreas Olofsson 2015-04-21 17:12:52 -0400
  • 72a3758dcf Bug fix, missing "data hold" stage Hadn't realized that the data needed to be held Need to look at this logic again! For now going back to old logic Andreas Olofsson 2015-04-21 17:10:51 -0400
  • a5c812e74c Wrong port direction on output Andreas Olofsson 2015-04-21 17:10:22 -0400
  • 1467498ec4 Integrating emesh memory module -This will flush out the final read response path Andreas Olofsson 2015-04-20 23:07:13 -0400
  • 16fcadb62b Adding emesh memory module (empty for now) Andreas Olofsson 2015-04-20 23:06:49 -0400
  • 905cab18ca Message box working... -More testing needed! Andreas Olofsson 2015-04-19 21:55:07 -0400
  • 2496548bad Memory read bug (clk floating) Andreas Olofsson 2015-04-19 21:54:22 -0400
  • d81ed1f99f MMU working... -Needs more testing Andreas Olofsson 2015-04-19 21:36:47 -0400
  • e8d15446fe Adding back awid, arid, lock to AXI interface Andreas Olofsson 2015-04-18 17:35:22 -0400
  • e0185bbfe5 Adding gtkwave signals file Andreas Olofsson 2015-04-18 16:42:34 -0400
  • a22215c99c Cleanup Andreas Olofsson 2015-04-18 16:26:32 -0400
  • 822dd6a6a0 Clock cleanup -Adding enable signal to clock out. Definitely right decision to keep separate bit from the divider field. -Fixed settings for to fit new register field -XILINX version is still broken!! Andreas Olofsson 2015-04-18 16:24:26 -0400
  • ac579a7f1a Fixed to fit with new register map Andreas Olofsson 2015-04-18 16:23:35 -0400
  • a33ecd5f34 Changed register map -Moved "groups" to E,D,C -Changed names to EL* (shorter is better, clear enough) -Moved order to fit logical operation during init -Moved embox registers to MMR group DONE! Andreas Olofsson 2015-04-18 16:21:45 -0400
  • 56ee0a2aaa ESAXI cleanup -widen address bus to 32 bits -blocking access to elink on ecfg access -fixing decoding for embox Andreas Olofsson 2015-04-18 16:18:41 -0400
  • 64811f828d Removed synchronizer on TXLCLK Andreas Olofsson 2015-04-18 16:17:44 -0400
  • 33229d4158 Adding manual test feature to testbench -This is as far as I go with fufu testing (random next) -Add basic test for cleaning up reads/writes -104 bit packet format for driving transactions, very useful Andreas Olofsson 2015-04-18 16:14:53 -0400
  • 19fcc8642e Clock divider fixup -changed to latest and hopefully final register config -fixed functional bugs (was broken..) -added xor for sensing change of clock frequency Andreas Olofsson 2015-04-18 16:12:43 -0400
  • 9ffc75e418 Adding basic elink read/write test Andreas Olofsson 2015-04-18 16:12:04 -0400
  • 5050d7678a Adding high level single ported memory Andreas Olofsson 2015-04-18 16:11:21 -0400
  • abadae8493 Simplifying register names Andreas Olofsson 2015-04-18 09:49:54 -0400
  • 56b85a2fc0 Prettifying format..starting to look decent Andreas Olofsson 2015-04-18 07:51:13 -0400
  • 4f7eac05ed Adding experimental README file Andreas Olofsson 2015-04-18 07:39:38 -0400
  • 8508ba362a Spell checking comments First time ever using spell cheker in EMACS. Hard to believe...but it's true! I am sure this speaks volume for how little I have commented my code over the years! Andreas Olofsson 2015-04-18 06:36:33 -0400
  • 6cf5fbb15e Cleaning up licenses for consistency -All files still GPLv3 -Placed at the bottom of the file (I am tired of looking at them!) Andreas Olofsson 2015-04-17 22:21:08 -0400
  • 56056dcf7d Adding documentation to elink top level module Andreas Olofsson 2015-04-17 22:10:14 -0400
  • 39f039564d Changed stimulus format to 32b_32b_32b_8b Andreas Olofsson 2015-04-17 16:02:23 -0400
  • 514528ca38 MILESTONE: Open souce simulation elink loopback working! Andreas Olofsson 2015-04-17 15:51:55 -0400
  • 130e0e5d16 Added profull HACK to async_fifo -this module needs rework -needs to have same capabilities as standard FPGA async fifos -remove this later Andreas Olofsson 2015-04-17 15:49:58 -0400
  • d03f31f469 Fixed odd/even copy past bug on DDR sampler Andreas Olofsson 2015-04-17 15:49:01 -0400
  • 0f96fae78a Fixed testbench bug (copy paste, RX not enabled)... Andreas Olofsson 2015-04-17 10:08:17 -0400
  • 584b5f7fb4 Getting all the clk config numbers aligned Not changing these again!! Andreas Olofsson 2015-04-16 22:48:31 -0400
  • 6e4a367617 Changing ESYSCLK definition (again.....) old implementation felt too "cutsy" this makes for a cleaner usage model (simple shift with param) also splitting out enable but, not making the CTIMER mistake again Andreas Olofsson 2015-04-16 22:31:36 -0400
  • 745397ff49 Added serial to parallel circuit + Xilinx BUFR Andreas Olofsson 2015-04-16 22:30:09 -0400
  • 1c884336b3 Renaming to something more clear (per user input...) Andreas Olofsson 2015-04-15 23:07:47 -0400
  • 45374fbfe4 Adding experimental OSERDESE2 model Experimental model, dirty design Bits are coming out and frame looks good.. Will continue with RX and debugging tomorrow Andreas Olofsson 2015-04-15 23:03:33 -0400
  • 1cba0409cd Xilinx models -adding ODDR model -configuring the ecfg (rx/tx/clk) in testbench Andreas Olofsson 2015-04-15 17:54:19 -0400
  • 649702a94d Cleaning up tx config register Andreas Olofsson 2015-04-15 17:53:50 -0400
  • cac278beb0 Fixing startup issues in transmit path: -adding reset signals to synchronizer to solve startup issues -setting config in test bench for speedup, default reg config now correct -fix (my) stupid bug in etx_arbiter -adding reset to fifo (todo: review this!) -reviewing "all red" from waveforms is a must. Red (x) on data is ok, but leaving them on control signals is asking for trouble. Better safe than sorry when it comes to reset. Andreas Olofsson 2015-04-15 16:33:20 -0400
  • c5177fb319 Fixed clock divider circuit -changed ecfg clock default values, elink default is now the PLL clock/128 coming out of reset -should work in any implementation? -still have to implement the Xilinx specific stuff Andreas Olofsson 2015-04-15 14:56:29 -0400
  • 9ca28b8f6f Continued work to create clean design: -pll bypass for clocks (customer request) -adding dividers on all clocks (tx/cclk) -adding reset block (clearer) -using commong clock_divider block -need to clean up divider block later today, slightly broken:-) Andreas Olofsson 2015-04-15 11:54:43 -0400
  • d233664605 Support files for fifo Andreas Olofsson 2015-04-14 23:56:59 -0400
  • 2a601bbb33 Adding platform agnostic dual ported memory and async fifo Andreas Olofsson 2015-04-14 23:56:00 -0400
  • 07889c9a84 Silly bug in access logic Looks like I was interrupt while coding.. Andreas Olofsson 2015-04-14 23:55:00 -0400
  • bfe5aa100d Running with "TARGET_CLEAN" Andreas Olofsson 2015-04-14 23:48:58 -0400
  • 2b5c4cfb89 Adding different data modes Good enough fufu testing... ..the next step is driving stimulus with transactor through Verilator.. Andreas Olofsson 2015-04-14 23:47:49 -0400
  • ed6ca3977f Adding back the "common" directory Andreas Olofsson 2015-04-14 23:22:29 -0400
  • c678b9191b AXI bug fixes -First bug was a typo. Cursing AXI for making every signal look exactly the same at first glance. Not good use practice -Second bug was sloppy. (removed pipeline stage on write data by mistake) Andreas Olofsson 2015-04-14 20:26:58 -0400
  • f0cda0e8b0 Verilator lint cleanup ~10 real bugs -mostly name mismatches and bit range mistakes Andreas Olofsson 2015-04-14 14:00:23 -0400
  • 98756ef5ef Fixed renaming bug..axi ready signal not working (would have been caught by verilator, time to lint...) Andreas Olofsson 2015-04-14 13:08:27 -0400
  • 2e5cf5a7d0 Added "fufu" DV environment for elink -Icarus for now, verilator comes next -Using our "standard" emesh interface ..here we go... Andreas Olofsson 2015-04-14 11:45:33 -0400
  • 7294925068 Removing unused signals from interface Andreas Olofsson 2015-04-14 11:44:31 -0400
  • b191c5910e Adding missing stubs Andreas Olofsson 2015-04-14 09:42:19 -0400
  • 6507834abc Adding fifo wrapper Andreas Olofsson 2015-04-14 09:06:08 -0400
  • 91a2a6644d Clean up of old files Andreas Olofsson 2015-04-14 08:32:04 -0400
  • c27e898d0d Man that's a lot of yak shaving.... Andreas Olofsson 2015-04-13 23:35:21 -0400
  • d2326c5a53 Changing emesh/elink transaction order Our "standard packet" order should be followed everywhere to ease verification and integration (standards are good fir reuse...): [0]=access [1]=write [3:2]=datamode [7:4]=ctrlmode [39:8]=dstaddr [71:40]=data [103:72]=upper-data (or srcaddr) Andreas Olofsson 2015-04-12 08:59:53 -0400
  • 6125989107 Removing folders that aren't needed anymore Andreas Olofsson 2015-04-11 00:14:43 -0400
  • b5dec2dfff Cleanup Removed useless common directory Fixed vivados permissions on file Andreas Olofsson 2015-04-11 00:12:57 -0400
  • ad96b8f563 Reorganizing files...too many folders after all. There is only one elink... Andreas Olofsson 2015-04-11 00:10:16 -0400
  • 007ad57548 Major cleanup, refactoring, and feature completion -adding clock bypass mode for esystx[12] -removing monitor feature on erx -remove loopback support from doc -add clock bypass mode for esysclk -shortening register names (descriptive enough) -added debug signal information -moving registers to elink -making elink version programmable (to support plug in boards) -reorganized debug signals and added stickys -added timeout for axi slave -removed embox status bit (redudant, don't poll status) -renamed EMBOX0-->EMBOXLO -moved datain interface straight to ecfg (cleanup) -changed etx arbiter priority to increase stability -created the esaxi_mux block -fixed some missing ports issues in stubs Andreas Olofsson 2015-04-11 00:04:18 -0400
  • 66b5f1693f Merge pull request from olofk/emmu_tb_fixes Andreas Olofsson 2015-04-10 09:42:15 -0400
  • 9ab1990cdf emmu: Refactor and add verilator testbench Olof Kindgren 2015-04-10 15:30:54 +0200
  • 0f6d7e6dec Merge branch 'master' of https://github.com/parallella/parallella-hw Andreas Olofsson 2015-04-09 12:11:44 -0400
  • c1ab24b5e3 Driving fall back model Andreas Olofsson 2015-04-09 12:11:26 -0400
  • ed7a8ffb44 Fixing bad merge This block will be completely redesigned Andreas Olofsson 2015-04-09 12:10:29 -0400
  • 9eb25a027e Updated dv environment Andreas Olofsson 2015-04-09 12:05:15 -0400
  • 1512f8e384 fixed broken links Andreas Olofsson 2015-04-09 11:41:44 -0400
  • 1fbd9f71df Starting work on a proper README file.. Andreas Olofsson 2015-04-09 09:59:54 -0400
  • b3525e3fee Reorg, cleanup Andreas Olofsson 2015-04-09 09:02:20 -0400
  • 31e2ee7be5 Removing old directory Andreas Olofsson 2015-04-09 08:59:34 -0400
  • 3bd470944a Removing unecessary levels of hiearchy Andreas Olofsson 2015-04-08 23:46:50 -0400
  • e41b6d328a Adding an elink block project file Andreas Olofsson 2015-04-08 23:46:06 -0400
  • 57aab65d52 Vivado run through -missed connections -mismatched bus widths -missing IP blocks -cleanup -proper DV starts tomorrow Andreas Olofsson 2015-04-08 23:40:16 -0400
  • 3105fe4bb4 Adding constraints Not sure if it's needed...still have to generate elink "ip" block Andreas Olofsson 2015-04-08 23:39:03 -0400
  • 746ef3f27e Adding stubs for IP blocks used in elink Andreas Olofsson 2015-04-08 23:38:36 -0400
  • 7c9b07748f Adding IP modules for elink Andreas Olofsson 2015-04-08 23:36:45 -0400
  • ab3da2471a Adding constants directory 1. Platform specific constants (xilinx vs altera) 2. Version specific constants Basically anything that affects `ifdefs Andreas Olofsson 2015-04-08 13:40:22 -0400
  • e45fd8b6f0 Fixing file permissions Verilog text files should not have execute permissions! Andreas Olofsson 2015-04-08 13:26:12 -0400
  • 1f076d19fc Fixing bus issue with datain/dataout signal Found in Vivado... Needed to connect up the wait signals properly on dataout/datain registers Andreas Olofsson 2015-04-08 13:20:25 -0400
  • 5d265888ff Refactoring and fixing bugs... -back and forth with emmu, memory is now inside (for good) -renamed clocks in etx to clarify -updated logic in protocol and disty -updated clock module ...one more review pass and we are ready for testing... Andreas Olofsson 2015-03-25 19:25:12 -0400
  • a826fbb713 Massive checkin... -this may break already broken projects -creates a Verilog top level (instead of using Vivado block level design) -integrates mmy and mailbox (not completely integrated) -compiles... -pours in all of the code from the archive (some new logic created) Andreas Olofsson 2015-03-24 20:44:03 -0400
  • 92c41a4739 Integrating Fred's changes Andreas Olofsson 2015-03-24 15:12:53 -0400
  • 89b0add048 Includes Fred's latest bug fixes (from project archive) Andreas Olofsson 2015-03-23 16:14:40 -0400