Aleksa Bjelogrlic
|
9644bf14e1
|
Added step to generate signing key
|
2022-10-10 20:56:12 -04:00 |
|
Aleksa
|
fbeaa9cd18
|
Updated stack-up and retuned length matching
|
2022-10-07 22:09:30 -04:00 |
|
Aleksa Bjelogrlic
|
129fd59d0c
|
Merge pull request #238 from EEVengers/HW/Aleksa/FPGA_Module_Rev2
Added FPGA Module Rev2
|
2022-09-28 23:46:38 -04:00 |
|
Aleksa
|
46cab5057c
|
Added Gerbers
|
2022-09-28 23:45:41 -04:00 |
|
Aleksa
|
b8181c7eee
|
Added FPGA Module Rev 2
|
2022-09-28 23:44:01 -04:00 |
|
Aleksa Bjelogrlic
|
ba69f0adb7
|
Merge pull request #234 from EEVengers/TS.NET
Added TS.NET
|
2022-05-11 19:34:03 -04:00 |
|
Aleksa
|
b3585d91f2
|
Added TS.NET
|
2022-05-11 19:31:29 -04:00 |
|
Aleksa
|
abaa0abde9
|
Removed git file for TS.NET
|
2022-05-11 19:30:06 -04:00 |
|
Aleksa
|
04f1332a50
|
Added TS.NET and removed scope control and electron software examples
|
2022-05-11 19:25:13 -04:00 |
|
Aleksa Bjelogrlic
|
3495a63714
|
Merge pull request #233 from EEVengers/FW/Aleksa/dso_top_fpga_module_Rev2_unsigned
Increased Serial FIFO Depth for PLL config
|
2022-05-11 19:17:20 -04:00 |
|
Aleksa
|
38debf466d
|
Increased Serial FIFO Depth for PLL config
|
2022-05-11 19:15:32 -04:00 |
|
Aleksa Bjelogrlic
|
e4bf17aca3
|
Merge pull request #232 from EEVengers/FW/Aleksa/dso_top_fpga_module_Rev2_unsigned
Firmware for FPGA module on Mainboard Rev2
|
2022-05-09 21:29:47 -04:00 |
|
Aleksa
|
5cad686e68
|
Firmware for FPGA module on Mainboard Rev2
|
2022-05-09 21:28:54 -04:00 |
|
Aleksa
|
44a4f41c40
|
Descriptive .bin file names
|
2022-05-09 20:26:28 -04:00 |
|
Aleksa Bjelogrlic
|
a5e1809fb4
|
Merge pull request #231 from EEVengers/FW/Aleksa/dso_top_fpga_module
Added unsigned fpga module firmware
|
2022-05-07 19:49:52 -04:00 |
|
Aleksa
|
c8216533c4
|
Added unsigned fpga module firmware
|
2022-05-07 19:48:48 -04:00 |
|
Aleksa Bjelogrlic
|
ee096c6549
|
Merge pull request #230 from EEVengers/FW/Aleksa/dso_top_fpga_module
Organizing Firmware Folder
|
2022-05-07 19:42:11 -04:00 |
|
Aleksa
|
59c3841b0d
|
Organizing Firmware Folder
|
2022-05-07 19:39:36 -04:00 |
|
Aleksa Bjelogrlic
|
406c9b5daf
|
Merge pull request #229 from EEVengers/FW/Aleksa/dso_top_unsigned
Organizing Firmware Folder
|
2022-05-07 19:33:42 -04:00 |
|
Aleksa
|
6b7bd2a50a
|
Organizing Firmware Folder
|
2022-05-07 19:30:45 -04:00 |
|
Aleksa Bjelogrlic
|
0807f481ac
|
Merge pull request #228 from EEVengers/HW/Aleksa/thunderscope_rev2
ThunderScope Rev.2 Complete
|
2022-05-02 18:32:21 -04:00 |
|
Aleksa
|
f2dd3dbea7
|
ThunderScope Rev.2 Complete
|
2022-05-02 18:28:47 -04:00 |
|
Aleksa Bjelogrlic
|
f9008ae100
|
Merge pull request #225 from profezzorn/libthunderscopehw
Libthunderscopehw
|
2022-03-06 09:06:55 -05:00 |
|
profezzorn
|
30b86f559b
|
work around fifo errors
|
2022-03-05 23:43:44 -08:00 |
|
profezzorn
|
1fc92c7b47
|
rename some things to make room for library with downscale & triggers
|
2022-03-05 21:32:10 -08:00 |
|
profezzorn
|
d9bcc1d8db
|
add stress test
|
2022-02-21 01:44:55 -08:00 |
|
profezzorn
|
09347e3d31
|
usage() fix
|
2022-02-20 01:09:54 -08:00 |
|
profezzorn
|
bb39482667
|
bugfix in hwdump, add thunderscope_hw_available() function and thunderscopehwcompensate
|
2022-02-20 01:09:28 -08:00 |
|
profezzorn
|
48f26b7c03
|
thunderscopehw bugfixes
|
2022-02-17 23:19:05 -08:00 |
|
profezzorn
|
2c2c5cb2a0
|
add --help to all example programs
|
2022-02-17 20:25:33 -08:00 |
|
Fredrik Hubinette
|
0b7e068b1e
|
make everything build on windows
|
2022-02-17 19:29:35 -08:00 |
|
Fredrik Hubinette
|
15c95b43bb
|
Merge branch 'libthunderscopehw' of https://github.com/profezzorn/ThunderScope into libthunderscopehw
|
2022-02-17 18:17:18 -08:00 |
|
profezzorn
|
191b10304e
|
swap fifo/datamover error bits
|
2022-02-17 09:56:43 -08:00 |
|
profezzorn
|
9cc7452839
|
add thunderscopehwbench and some minor fixes
|
2022-02-16 23:44:12 -08:00 |
|
profezzorn
|
f33a25602e
|
various updates
|
2022-02-16 21:10:30 -08:00 |
|
profezzorn
|
b6c9e37abd
|
fix dc couple options
|
2022-02-16 10:21:41 -08:00 |
|
Aleksa
|
ff60606203
|
Updated FPGA Module Schematics
|
2022-02-15 22:55:43 -05:00 |
|
Aleksa
|
666daf564f
|
Added Latest Main Board Schematic
|
2022-02-15 22:50:42 -05:00 |
|
Aleksa
|
9326d8e1b0
|
Firmware for new FPGA module
|
2022-02-13 12:05:22 -05:00 |
|
profezzorn
|
454052c050
|
start calibration program
|
2022-02-13 01:04:00 -08:00 |
|
Aleksa
|
257a5dbada
|
Fixed ADC inversion
|
2022-02-12 22:24:32 -05:00 |
|
Aleksa
|
1828184354
|
removed two's compliment conversion in FPGA
|
2022-02-07 19:15:46 -05:00 |
|
profezzorn
|
dd17422182
|
convert signed bytes to unsigned bytes since 8-bit wav files are unsigned
|
2022-02-06 22:12:21 -08:00 |
|
profezzorn
|
ff6df7e2ea
|
invert relay
|
2022-02-06 21:58:24 -08:00 |
|
profezzorn
|
3d89cb41f1
|
adc bugfixes
|
2022-02-06 19:18:13 -08:00 |
|
Aleksa
|
91a88f978e
|
Some register fixes, still stalls on read with ThunderScope board though
|
2022-02-06 14:15:34 -05:00 |
|
Aleksa
|
06c0310e37
|
Fix return value on windows read_handle function
|
2022-02-01 22:16:09 -05:00 |
|
profezzorn
|
79acd473ee
|
several bugfixes, now getting ramp data
|
2022-01-31 22:57:56 -08:00 |
|
Aleksa
|
61120acf30
|
Changed FIFO_ISR Value to use uppermost byte
|
2022-01-31 22:40:17 -05:00 |
|
profezzorn
|
75d830a778
|
fix read32 byte order
|
2022-01-31 19:07:18 -08:00 |
|