AllSpiceMirrors/ThunderScope
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Rev5_KiCad
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1063 Commits

Author SHA1 Message Date
Aleksa Bjelogrlic
07e75ae1d8 IOCrest Interposer Out to Fab 2025-04-16 12:42:12 -04:00
Aleksa Bjelogrlic
60f8b34482 Merge remote-tracking branch 'origin/Rev5_KiCad' into Rev5_KiCad 2025-04-16 12:17:50 -04:00
Aleksa Bjelogrlic
e8f907dd43 JoneyTech Interposer out to fab 2025-04-16 12:17:43 -04:00
Aleksa Bjelogrlic
9c5d3b6d7e Interposer out to fab 2025-04-16 12:17:11 -04:00
Aleksa Bjelogrlic
1ffa4a65f3 Rev 5 out to fab 2025-04-15 18:13:54 -04:00
Aleksa Bjelogrlic
11197956e1 Final review before fab 2025-04-15 14:47:11 -04:00
Aleksa Bjelogrlic
65b5a21b1f DRC Clean 
Just need to double check delay matching and look over bottom layer copper before release to fab
 2025-04-15 00:59:28 -04:00
Aleksa Bjelogrlic
26df70d57e Final Polish WIP 2025-04-14 15:53:12 -04:00
Aleksa Bjelogrlic
e654341526 USR and SYNC LVDS Delay Tuning Complete 2025-04-13 18:14:13 -04:00
Aleksa Bjelogrlic
cc3650c42d Via Stitching WIP 
Unmatched PGA Diff pairs, will need to redo that
 2025-04-12 16:06:33 -04:00
Aleksa Bjelogrlic
b80d088d7c ADC LVDS Pairs Delay and Skew Matched 2025-04-11 19:45:25 -04:00
Aleksa Bjelogrlic
da70972332 Moved CLK25 to P side of MRCC pair 
Swapped with LED_R
 2025-04-11 12:08:19 -04:00
Aleksa Bjelogrlic
e8683f8c2e Skew Matched PCIe Traces 2025-04-11 00:13:35 -04:00
Aleksa Bjelogrlic
df1cd2e7a7 Delay Matched PGA Outputs 2025-04-10 21:55:50 -04:00
Aleksa Bjelogrlic
80b6bae41a Via stitching in progress 2025-04-09 23:39:06 -04:00
Aleksa Bjelogrlic
ac2b6d631e Added Bottom Silk TP Labels 2025-04-09 19:39:31 -04:00
Aleksa Bjelogrlic
f40ddbb82b Added test points on all shunts that didn't have them 2025-04-08 17:24:26 -04:00
Aleksa Bjelogrlic
0cf3063b8f Added more test points 
Everything on Bank 14 covered except HWIDs, VARIENT, and PUDC
 2025-04-07 16:19:28 -04:00
Aleksa Bjelogrlic
533850988e Reversed Channel Order 
In channel blocks, net labels, and reference designators
 2025-04-07 13:53:55 -04:00
Aleksa Bjelogrlic
8a462c1705 Merge remote-tracking branch 'origin/Rev5_KiCad' into Rev5_KiCad 2025-04-07 01:14:00 -04:00
Aleksa Bjelogrlic
3ba7b49437 GND connections finished 
Also increased trace spacing where possible
 2025-04-07 01:13:52 -04:00
Aleksa Bjelogrlic
031d8ee9b3 Increased trace spacing where possible 2025-04-07 01:13:13 -04:00
Aleksa Bjelogrlic
c32c0c2029 Finished ACQ power planes 
Working on GND planes now
 2025-04-06 16:40:08 -04:00
Aleksa Bjelogrlic
7584a7e23d All FPGA power planes done 
Only ADC + Clock gen power left before GND and delay matching
 2025-04-05 14:01:11 -04:00
Aleksa Bjelogrlic
b580798762 Power planes WIP 2025-04-04 14:25:25 -04:00
Aleksa Bjelogrlic
79b35a20c8 Finished all signal routing 
PWR, GND and Length Tuning remains
 2025-04-03 20:52:06 -04:00
Aleksa Bjelogrlic
d2235e8740 Final signal routing WIP 2025-04-01 19:28:58 -04:00
Aleksa Bjelogrlic
a7292c5a8a Routed ADC and Clock Gen 2025-03-30 18:26:57 -04:00
Aleksa Bjelogrlic
c1be308336 Placed and Routed QSPI 
All decoupling and FPGA support components placed
 2025-03-29 16:24:52 -04:00
Aleksa Bjelogrlic
10f9c97653 Placed most of the FPGA decoupling 2025-03-29 01:45:52 -04:00
Aleksa Bjelogrlic
cd212bd7c9 Diff pair cleanup and rerouting 2025-03-28 23:20:34 -04:00
Aleksa Bjelogrlic
e5365d0c16 Changed refresh variable name 2025-03-27 18:49:00 -04:00
Aleksa Bjelogrlic
2b4dbd54a7 Got delay tuner to write to rules file 2025-03-27 18:46:35 -04:00
Aleksa Bjelogrlic
6622021a9f Added first pass interactive delay tuner 2025-03-27 00:34:01 -04:00
Aleksa Bjelogrlic
555652f44c Finished routed all diff pairs 
Still need to length and skew match them
 2025-03-26 01:48:59 -04:00
Aleksa Bjelogrlic
a0e3dcff0b Merge remote-tracking branch 'origin/Rev5_KiCad' into Rev5_KiCad 2025-03-25 18:20:18 -04:00
Aleksa Bjelogrlic
1d8c493b85 Started routing all other diff pairs 
I miss Altium :(
 2025-03-25 18:20:10 -04:00
Aleksa Bjelogrlic
99b85d1774 Started diff pair routing 
I miss Altium :(
 2025-03-25 18:19:22 -04:00
Aleksa Bjelogrlic
4e97e82a2f LVDS Routing WIP 
Also placed PCIe stuffing options
 2025-03-25 00:40:45 -04:00
Aleksa Bjelogrlic
bac0f98dd9 Finished custom routing rules 
Also cleared up a bunch of DRC errors
 2025-03-24 00:49:05 -04:00
Aleksa Bjelogrlic
b9fc26308a Playing with Custom Design Rules 2025-03-23 13:17:32 -04:00
Aleksa Bjelogrlic
e3eddc9873 Finished Routing ACQ regulators 2025-03-23 00:51:20 -04:00
Aleksa Bjelogrlic
cea3212237 Routing in progress, minor SCH changes 
Stiffer I2C Pullups, more 100nF changed to 1uF
 2025-03-22 17:05:57 -04:00
Aleksa Bjelogrlic
d03db415d6 Misc WIP 
Changed ADC decoupling, improved acq reg placement, etc.
 2025-03-21 23:23:21 -04:00
Aleksa Bjelogrlic
24bbcac181 Finished Routing FE Voltage Regs 2025-03-21 18:21:41 -04:00
Aleksa Bjelogrlic
3f307ab487 Routed FE Support Components 2025-03-20 23:22:59 -04:00
Aleksa Bjelogrlic
f64a908e49 Fixed Hole Spacing on IOCrest Interposer 
Also added clearance holes for heatsink push pins and grounding lug
 2025-03-18 20:58:41 -04:00
Aleksa Bjelogrlic
aadb553d17 Merge remote-tracking branch 'origin/Rev5_KiCad' into Rev5_KiCad 2025-03-17 21:38:59 -04:00
Aleksa Bjelogrlic
a13d0954f2 Fixed Net Swaps 
On Sync_REn & SYNC_DE as well as MGT_CLK1
 2025-03-17 21:38:50 -04:00
Aleksa Bjelogrlic
a40f933cef Fixed Net Swaps 
On Sync_REn & SYNC_DE as well as MGT_CLK1
 2025-03-17 21:34:57 -04:00